The Designer's Guide Community Forum

The Designer's Guide Community Forum
https://designers-guide.org/forum/YaBB.pl
Design Languages >> Verilog-AMS >> [Help] error on simulation about verilogA block
https://designers-guide.org/forum/YaBB.pl?num=1299575992

Message started by Patrick520 on Mar 8^th, 2011, 1:19am

Title: [Help] error on simulation about verilogA block
Post by Patrick520 on Mar 8^th, 2011, 1:19am

Hi. I am new to Cadence IC5141. I am doing a simple simulation. I use Cadence IC5141 on RHEL5.4.
I use model writer to write a delay cell, the verilogA code is listed here:

"
`include "discipline.h"
`include "constants.h"

module delay_elem (vin, vout);
input vin;
output vout;
electrical vin, vout;

parameter real td = 1.0n from (0:inf);

analog begin
V(vout) <+ absdelay(V(vin), td );
end
endmodule
"

And I use a pulse source from analogLib to give this delay cell pulses. And the delay cell is connected to a 50ohm resistor. I use the ADE (spectre) to simulate the cell.

I chose tran analysis.

However, there is error here:

Error found by spectre during circuit read-in.
"input.scs " 9 :Top-level parameter 'm' must be initialized with a value or expresstion.
Warning from spectre during circuit read-in.
"input.scs" 10: parameter name 'm' is researved for the subcircuit multiplicity factor. So a formal parameter of that name is ignored.

Error found by spectre during circuit read-in.
"input.scs" 16 : statementis not in spectre format.
Warning from spectre during AHDL read-in.
"/home/zxr/circuit_design/MyResearch/delay_1ns/veriloga/veriloga.va", line 28: warning: `(abs)delay()' dose not account for phase shift in small-signal analysis.

My question is about the variable m. I never set the variable m. And I didnot describe it in the delay cell.

Can anyone help me?

Title: Re: [Help] error on simulation about verilogA block
Post by rfidea on Mar 8^th, 2011, 3:53am

About the m. Check the parameters your other components, the pulse source and resistor it there is any m there. m is used as multiplier for resistors. Check the resistor parameters carefully.

If you do not find the problem, please post your netlist, which is the file input.scs

Title: Re: [Help] error on simulation about verilogA block
Post by sheldon on Mar 8^th, 2011, 5:14am

Patrick,

Have you looked at the netlist? Is the variable used in the
netlist?

Best Regards,

Sheldon