The Designer's Guide Community Forum

The Designer's Guide Community Forum
https://designers-guide.org/forum/YaBB.pl
Design Languages >> Verilog-AMS >> can a module instantiation identify itself?
https://designers-guide.org/forum/YaBB.pl?num=1300120504

Message started by altaj on Mar 14^th, 2011, 9:35am

Title: can a module instantiation identify itself?
Post by altaj on Mar 14^th, 2011, 9:35am

I have a trigger set up to stop simulation and issue a warning if specific clock edges get to close to each other. I'm doing this to cover the case where verilog-a will do something that a transistor circuit will not, such as trigger a DFF on coincident, or very close, CLK and D edges.

Question: Is it also possible to have the identity of the specific instantiation of the module reported?

Title: Re: can a module instantiation identify itself?
Post by Ken Kundert on Mar 14^th, 2011, 10:17pm

Yes, use %M in the message.

-Ken