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Design >> Analog Design >> Clock of the SC CMFB
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Message started by LeonQQ on Mar 17^th, 2011, 10:34am

Title: Clock of the SC CMFB
Post by LeonQQ on Mar 17^th, 2011, 10:34am

Hi folks,

I am designing a fully differential OTA used in a switched capacitor (SC) integrator. I want to use an SC CMFB for the OTA.

I wonder if I should use a much faster (say 4x faster) clock for the CMFB than the clock for the integrator, since the CMFB needs a few clock cycles to settle to the desired common-mode voltage.

I checked quite a few papers, but found no one mentioning the clock speed for the CMFB.

Thank you all in advance.

Leon

Title: Re: Clock of the SC CMFB
Post by Rakesh on Mar 17^th, 2011, 3:56pm

Hi,
I think it would be fine provided u maintain that switch of the integrator and the switch of the CMFB not close at the same time. Correct me if i am wrong
Rakesh

Title: Re: Clock of the SC CMFB
Post by LeonQQ on Mar 17^th, 2011, 4:59pm

Hi Rakesh,

Thank you for your reply. Assume we use the same non-overlap clocks for both CMFB and the integrator. Assume PHI1 is for sampling and PHI2 is for integrating.

The OTA only needs to be available in PHI2. But the question is if the common mode of the OTA can settle fast enough to the desired value within PHI2?

Leon

Title: Re: Clock of the SC CMFB
Post by Rakesh on Mar 17^th, 2011, 5:28pm

Hi Leon,
See during Phi1 u r sampling. During that time my SC CMFB should work and set the common mode of the OTA. During Phi2 we have the desired common mode voltage on the OTA and hence it can integrate. We need to design the CMFB such that the common mode settle within Phi1.
Correct me if i am wrong
Rakesh

Title: Re: Clock of the SC CMFB
Post by subgold on Mar 24^th, 2011, 3:54am

i doubt if it is a good idea.

provided ur targeted common mode voltage is fixed and not changed at every cycle, then the problem you mentioned is more like a startup issue. once it settles to the desired common mode level, the SC CMFB will hold it and will not change any more, because theoritically there will be no more charge/discharge happening in the lossy integrator formed by the SC CMFB.

from a practical point of view, how do you obtain the 4x clock? it could be very costly. if you already have such a clock available, then why not use it to enhance the performance of the SC integrator itself?

Title: Re: Clock of the SC CMFB
Post by loose-electron on Mar 24^th, 2011, 6:37am

what you are talking about is commonly referred to as "phased clocks" or "interleaved clocks"