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Design >> Analog Design >> Funny issue with the CMFB of a miller compensated amplifier
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Message started by tron_123 on Mar 20^th, 2011, 10:20am

Title: Funny issue with the CMFB of a miller compensated amplifier
Post by tron_123 on Mar 20^th, 2011, 10:20am

Hi,

While stabalizing continuous time CMFB of a two stage miller compensated amplifier, I am saw some funny results with the CMFB's AC response. These results are attached as a pdf with this post. For the simplicity, I made a single ended input output amplifier replicating the same CMFB path and reproduced the same results.

I am using 130nm digital transistors from a reputed foundry. The observations are made by chaging the size of the PMOS tail current source alone. During these obeservations, all trasistors are in saturation with sufficient margins. Test bench to test the AC response is also mentioend in the attachment. For all the tests, load capacitance is 400f.

There are the observations:

1. There is a peaking in the gain responce at around 10MHz which does not come in my calculations at all.
2. When W/L of tail transistor is changed from 2u/1u to 3u/1u, there is a considerable change in the phase response which I don't expect to happen.
3. When I replace EITHER the first or second stage's PMOS tail transistor with the ideal current source and equivalent parasitics, I get the correct response.

I don't understand why AC respnse behave normally with either of the PMOS tails is replace with ideal current sources. I also don't understand the peaking and sudden phase shift.

Please shed some light on these results, tell me if there is some issue with my testbench, my understanding or my process.

Regards, Tron

Title: Re: Funny issue with the CMFB of a miller compensated amplifier
Post by aaron_do on Mar 20^th, 2011, 6:31pm

Hi,

how are you setting pbias_tail? Your pbias_tail nodes are joined together, and form a positive feedback loop through their Cgd capacitances. When you replace either PMOS with an ideal current source, this positive feedback loop goes away. This could be the problem. If you bias pbias_tail with an ideal voltage source, it might also go away.

cheers,
Aaron

Title: Re: Funny issue with the CMFB of a miller compensated amplifier
Post by Alexandar on Mar 21^st, 2011, 1:23am

I have pretty much the same doubt as aaron_do. As far as I can see it is the only loop present in your amplifier. So how do you bias your upper p-mos transistors? You could check whether some capacitance on that node kills this peaking.

Title: Re: Funny issue with the CMFB of a miller compensated amplifier
Post by tron_123 on Mar 22^nd, 2011, 6:03am

Thanks aaron_do and Alexandar,
It is the same problem as you mentioned. When I break the positive feedback loop coming from the PMOS bias, the peaking disappears. I am now planning to make a separate bias for the output stage.