The Designer's Guide Community Forum

The Designer's Guide Community Forum
https://designers-guide.org/forum/YaBB.pl
Design Languages >> Verilog-AMS >> Contribution statement
https://designers-guide.org/forum/YaBB.pl?num=1300988590

Message started by elecky mess on Mar 24^th, 2011, 10:43am

Title: Contribution statement
Post by elecky mess on Mar 24^th, 2011, 10:43am

Hello, I'm a newbie to Verilog-AMS, and what I am currently trying to do is to assign some value for a voltage at a port or across a branch in some given condition. For example, my Verilog-A code would be like

Code:

parameter real c = 1.2;
analog begin

...

@( condition 1 )
V(a,b) <+ c;

...

if ( condition 2 )
V(a,b) <+ 0;

...

end

I actually made something similar to this, and tried to simulate it in Cadence Hierarchy Editor. It uses NC Verilog simulator, right? But whenever I tried simulation, I got errors and they all pointed the lines where "<+" operators were used. The error messages were like

Code:

" ../veriloga.va line xx: Encountered a contribution statement embedded in an analog event.
Remove the contribution statement from the analog event."

Here I got confused. As far as I know, a contribution statement can actually be used only in an analog event, and it is used to assign an expression to a voltage or a current at a port or branch. I think any real number or any parameter as used in my code is a legitimate expression. If I am right, what's wrong with my code?

Title: Re: Contribution statement
Post by Geoffrey_Coram on Mar 25^th, 2011, 5:08am

[quote author=eleckymess link=1300988590/0#0

Code:

@( condition 1 )
V(a,b) <+ c;
end

[/quote]

The "@" is what makes this an analog event.

Quote:

It uses NC Verilog simulator, right?

NC Verilog is a digital Verilog simulator; you are using AMS, so I think you probably have Spectre running this module.

Quote:

You may be thinking digitally. The analog block of an AMS module is evaluated at every timepoint of the transient analysis. On some of those timepoints, the @(analog_event) will fire, and the simulator would try to make the contribution, but on other timepoints, what do you want to happen?

You probably want something like

Code:

@(initial_step)
vout = 0;
@( condition1)
vout = c;

V(a,b) <+ transition(vout);

where now, the contribution is not conditional: it always establishes a voltage-source branch between a and b, but the voltage it enforces varies.