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https://designers-guide.org/forum/YaBB.pl Design Languages >> Verilog-AMS >> Solving ODE in Verilog-AMS https://designers-guide.org/forum/YaBB.pl?num=1301308727 Message started by Sumit Adhikari on Mar 28th, 2011, 3:38am |
Title: Solving ODE in Verilog-AMS Post by Sumit Adhikari on Mar 28th, 2011, 3:38am Does anybody has any idea, if it is possible to solve an ODE in Verilog-AMS ? All my tries failed. Regards, Sumit |
Title: Re: Solving ODE in Verilog-AMS Post by boe on Mar 28th, 2011, 8:18am Sumit, What do you want to achieve? It should be obvious how to solve an ODE if you use a time derivative, so I suppose that's not what you want. B O E |
Title: Re: Solving ODE in Verilog-AMS Post by Sumit Adhikari on Mar 28th, 2011, 8:52am You are absolutely correct, I also thought that way. I am in need to solving current and voltage equations as the way I wish and add them with some other currents/voltages. I want to study transport equations modified quantum mechanical effects in DSM technology, for this Verilog-AMS is good, as I have good controllability. For a warm up I took SHM equation (ddt(ddt(V(p,n))) <+ -k * V(p,n), which should give me sinusoidal out put like a0*sin(wt). Following is the code : `include "discipline.vams" `include "constants.vams" module oscillations_ode (p, n); inout p ; inout n ; electrical p ; electrical n ; electrical d_1 ; electrical d_2 ; parameter real k = 10000.0 ; real reff; analog begin//{ //@(initial_step) @(initial_step("dc", "ac", "tran", "xf")) begin//{ V(p,n) <+ 1.0 ; V(d_1,n) <+ 0.0 ; V(d_2,n) <+ 0.0 ; end//} V(d_1,n) <+ ddt(V(p,n)) ; V(d_2,n) <+ ddt(V(d_1,n)) ; V(d_2,n) <+ -k*V(p,n) ; end //} endmodule output of this block (p) is driving a small parallel load of a resistor and a capacitor. The solver is running, but I am always getting 0 output. Do not understand why >:( Regards, Sumit |
Title: Re: Solving ODE in Verilog-AMS Post by boe on Mar 29th, 2011, 7:39am Sumit, your code is wrong. Code:
Code:
Code:
This works with my simulator. B O E PS: You misused the contribution statement. It is not an assignment. |
Title: Re: Solving ODE in Verilog-AMS Post by Sumit Adhikari on Apr 1st, 2011, 11:56am Thanks for pointing out my mistake. Regards, Sumit |
Title: Re: Solving ODE in Verilog-AMS Post by Sumit Adhikari on Apr 1st, 2011, 11:58am Thanks for pointing out my mistake. Regards, Sumit |
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