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Design Languages >> Verilog-AMS >> Oscillator different simulation Results SMASH - ADE
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Message started by Zorro on Mar 29^th, 2011, 3:18am

Title: Oscillator different simulation Results SMASH - ADE
Post by Zorro on Mar 29^th, 2011, 3:18am

Hello Everybody,

I am trying to model a simple oscillator in verilogA.

The main restrictions are:

1. It oscillates only if the Supply Voltage is bigger than a threshold (1V) and if the stby Signal is less than (Supply Voltage)/2.

2. If the required conditions are met (state signal is high), the cell oscillates after a delay of startup_delay.

So far so good.

The simulation of the circuit in SMASH shows the expected result.

However, if I use the same verilogA Model in ADE it doesn't work correctly.

Can please someone have a look at it? I was thinking maybe it is because of the simulation settings but in ADE but I really don't think so.

Please check the internal signal slope.

Attached you will find:

a. The verilogA Code (it's verilogAMS but limited to verilogA).

b. The Testbench (spice Netlist)

c. Some screenshots from SMASH showing the expected result.

The problem is when simulating the oscillator in ADE I don't get some pulses, only a peak.

Thanks for your support

Title: Re: Oscillator different simulation Results SMASH - ADE
Post by Zorro on Mar 29^th, 2011, 3:19am

this is the verilogA code:

`include "disciplines.vams"
`include "constants.vams"

module oscillator (stby, clk_1mhz, vdd_1v8, vss);

inout stby, clk_1mhz, vdd_1v8, vss;
electrical stby, clk_1mhz, vdd_1v8, vss;

parameter real fc = 1e6 from (0:inf); // Frequency of the Oscillator (Hz)
parameter real kv = 0.0; // Gain (Hz/V)
parameter real duty = 0.5 from (0:1); // Duty Cycle. Example: duty = 0.5
parameter real threshold=1.0; // vdd_1v8 must be higher than threshold for the oscillator to operate

parameter real td=0.1n; // Default Delay Time for Transitions
parameter real tr=0.1n; // Default Rise Time for Transitions
parameter real tf=0.1n; // Default Fall Time for Transitions
parameter startup_delay = 0.2u; // Startup Delay Time for Signal clk_1mhz

parameter real current_on=3u; // Current Consumption when Cell is ON
parameter real current_off=0.2u; // Current Consumption when Cell is OFF (or not correctly biased)

real vdd_1v8_ok, stby_ok, state, t1, icc, slope, vout_temp;

// only for test purposes
electrical slope_e, state_e;

analog begin
@(initial_step) begin
slope = 1.0;
state = 0.0;
t1 = 0.0;
end

// Monitoring the vdd_1v8 Signal
@(cross( V(vdd_1v8) - threshold, 0) or initial_step)
;
if (V(vdd_1v8) > threshold) vdd_1v8_ok = 1.0; // Supply Voltage is higher than the mimimum threshold
else vdd_1v8_ok = 0.0; // Supply Voltage is lower than the mimimum threshold

// Monitoring the stby Signal
@(cross( V(stby) - (V(vdd_1v8)/2), 0) or initial_step)
;
if (V(stby) < (V(vdd_1v8)/2)) stby_ok = 1.0 * vdd_1v8_ok; // Oscillator is enabled
else stby_ok = 0.0 * vdd_1v8_ok; // Oscillator is disabled

// Monitoring the state (ON/OFF) of the oscillator
@(cross( vdd_1v8_ok - 0.5, 0) or cross( stby_ok - 0.5, 0) or initial_step)
;
if (vdd_1v8_ok*stby_ok>0.5) begin
state = 1.0;
end else begin
state = 0.0;
end

// Controlling the slope Signal
@(cross( state - 0.5, +1)) begin
t1 = $abstime;
slope = -1.0;
end
if (state>0.5) begin
@(timer(t1+startup_delay, duty/fc)) slope = -1.0 * slope;
end else begin
slope = slope;
end

// Current Consumption
@(cross( state - 0.5, 0))
;
if (state>0.5) icc = current_on;
else icc = current_off;
I(vdd_1v8, vss) <+ icc;

vout_temp = 0.5 * (slope + 1.0) * state;

// Output Signals
V(clk_1mhz) <+ vout_temp * V(vdd_1v8);

// only for test purposes
V(slope_e) <+ slope;
V(state_e) <+ state;

end

endmodule

Title: Re: Oscillator different simulation Results SMASH - ADE
Post by Zorro on Mar 29^th, 2011, 3:20am

and this is the file for the testbench:

.lib oscillators_wo_idt.vams

Vsupply vdd_1v8 0 PWL 0 0 200n 1.8 875n 1.8 900n 1.2 925n 1.8 1.8u 1.8 2.9u 1.8 3u 0 3.5u 0 3.6u 1.8 //6.6u 1.8 6.61u 0 7.6u 0 7.61u 1.8
Vstby stby 0 PWL 0 1.8 400n 1.8 500n 0 1.75u 0 1.775u 0.8 1.8u 0 5u 0 5.1u 1.8 5.6u 1.8 5.7u 0
xosc1 stby clk_1mhz vdd_1v8 0 oscillator

Thank you for your help!
:)- Zorro

Title: Re: Oscillator different simulation Results SMASH - ADE
Post by Zorro on Mar 29^th, 2011, 4:11am

this is the simulation result from ADE.

the slope signal reacts (goes high) when conditions are met and after the specified delay but then it goes low inmediately. It should remain high for half the period.

if you compare the results in SMASH are as expected.

How can this be?

thank you!

Title: Re: Oscillator different simulation Results SMASH - ADE
Post by Geoffrey_Coram on Apr 6^th, 2011, 9:44am

This looks suspicious to me:

Code:

if (state>0.5) begin
@(timer(t1+startup_delay, duty/fc)) slope = -1.0 * slope;
end else begin
slope = slope;
end

I don't think it's a good idea to put a timer inside an if statement. I'd reverse it:

Code:

@(timer(t1+startup_delay, duty/fc)) begin
if (state>0.5) begin
slope = -1.0 * slope;
end
end