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Design >> RF Design >> best RF PA Floorplan location
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Message started by makelo on Mar 30^th, 2011, 9:57am

Title: best RF PA Floorplan location
Post by makelo on Mar 30^th, 2011, 9:57am

I would like to hear peoples thoughts about the best location for an RF power amplifier in an SoC.

I am floorplanning an RF transceiver with a power amplifier that sinks ~350mWatt of quiescent power. I can place the PA either in the corner of the die or in the middle along one edge. Which is best?

In both locations there is plenty of room for multiple ground and Vdd bondwires. The CMOS SoC is somewhat large and contains considerable digital real estate. My main concern is about die stress, reliability and getting the heat out. Is one location better than the other for these issues?

Thanks,
Makelo

Title: Re: best RF PA Floorplan location
Post by loose-electron on Mar 30^th, 2011, 7:06pm

model in your bonding and package impedances - all power and ground pins- with that you are going to see the PA do some pretty crazy things to the power-ground-substrate

Go from there.