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https://designers-guide.org/forum/YaBB.pl Design Languages >> Verilog-AMS >> timer function problem https://designers-guide.org/forum/YaBB.pl?num=1301559713 Message started by Zorro on Mar 31st, 2011, 1:21am |
Title: timer function problem Post by Zorro on Mar 31st, 2011, 1:21am Hi all, I need some help to find out what is wrong with my code. I want a signal "slope" to oscillate only when "state" is high. The oscillation must start after a delay "startup_delay". when state is low, there is no oscillation and slope retains its value. the simulation in ADE reacts well for the first cross of state in the positive direction. you can see slope changes after the specified delay and continues oscillating with the specified frequency while state is high. but for the second cross slope changes after the specified delay but goes automatically to its previous value so instead of having a pulse of lenght period/2 I only have a peak. here is the code for the timer declaration: ... real state, slope; integer armed; analog begin @(initial_step) begin slope = 1.0; state = 0.0; t1 = 0.0; end // Controlling the slope @(cross( state - 0.5, +1)) begin t1 = $abstime; slope = -1.0; armed=1; end @(cross( state - 0.5, -1)) begin slope = slope; armed=0; t1=0; end if (armed) begin @(timer(t1+startup_delay, duty/fc)) begin slope = -1.0 * slope; end end ... end Any suggestion? Thank you. |
Title: Re: timer function problem Post by boe on Mar 31st, 2011, 2:14am Zorro, Timer event statements inside conditional statements are not allowed (at least by the tools I use). B O E [Added] PS: As the start time of the timer event may be dynamic, it is not necessary to have it inside an if statement. |
Title: Re: timer function problem Post by Zorro on Mar 31st, 2011, 3:08am thanks for the reply boe, if I simulate in SMASH I get what I expect. if I simulate in ADE then I have this problem. in both the timer event statements inside conditional statements are allowed. May I ask what simulator do you use? then I don't know if the problem is the code itself or the simulator. If I modify the timer function like this: @(timer(t1+startup_delay, duty/fc, 1/fc)) then the pulses are recognized correctly in ADE, but not the delay i.e. it starts to oscillate exactly when the state signal goes high. I don't know exactly how to limit this new parameter <timeTol>. (Designer's Guide to VerilogAMS, page 206) PS: As the start time of the timer event may be dynamic, it is not necessary to have it inside an if statement. ummm... does it mean that it is not possible to, let's say "reset" the start of the timer function? every time state goes high I am sampling a new t1...but if it is so, this t1 is only being considered the first time and the other t1s are ignored. from "Designer’s Guide to Verilog-AMS", page 78: "The timer function produces an event at the (absolute) time given by its first argument, and if its second argument is present, it will produce subsequent events with a period equal to the value of the second argument." if you have any suggestion please let me know. thanks and regards! Zorro |
Title: Re: timer function problem Post by boe on Mar 31st, 2011, 3:52am Zorro wrote on Mar 31st, 2011, 3:08am:
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Title: Re: timer function problem Post by boe on Mar 31st, 2011, 9:27am Zorro, Did you notice the post http://www.designers-guide.org/Forum/YaBB.pl?num=1299882714? [edit]Uses a non-periodical timer. Might cause fewer portability issues.[/edit] B O E |
Title: Re: timer function problem Post by Geoffrey_Coram on Apr 7th, 2011, 7:14am What if you change if (armed) begin @(timer(t1+startup_delay, duty/fc)) begin slope = -1.0 * slope; end end to @(timer(t1+startup_delay, duty/fc)) begin if (armed) begin slope = -1.0 * slope; end end ? |
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