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Design >> Analog Design >> Reference buffer for ADCs
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Message started by tron_123 on Apr 6^th, 2011, 7:18am

Title: Reference buffer for ADCs
Post by tron_123 on Apr 6^th, 2011, 7:18am

Dear Friends,

I am designing a differential reference buffer for high speed SAR ADC (25Msps, 8 bit). Depending on the settling requirement, I can derive the specs such as UGB and Bandwidth. But it turns out that depending on the buffer architecture for example miller compensated or load compensated, I can trade-off area with power for the same settling. I only know these two architectures but I am sure that there could be others out there.

I would like to know as how to decide on the reference buffer architecture based on the frequency of operation, resolution and the type of ADC. It would be great if anyone of you can also point me to the paper or book where this thing is discussed.

Thanks
-Tron

Title: Re: Reference buffer for ADCs
Post by tron_123 on Apr 9^th, 2011, 10:47pm

Bounce!

I apologize for asking a very trivial question here, but I am a beginner in analog design and any insight into the reference buffer facts will be very helpful.

-Tron

Title: Re: Reference buffer for ADCs
Post by loose-electron on Apr 10^th, 2011, 8:40pm

I think the reason you are not getting a lot of answers here is because the question is too general.

Suggest that you start reading papers and textbooks on the subject. Depending on where you are, there are classes at Universities on the subject as well.