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Design >> Analog Design >> noise in delta sigma modulator design
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Message started by naderi on Apr 7^th, 2011, 7:03am

Title: noise in delta sigma modulator design
Post by naderi on Apr 7^th, 2011, 7:03am

Hello all,

In design of a delta sigma modulator, if we look for a SNDR>85 dB for a 10 kHz bandwidth (BW), then the output integrated in-band noise (IBN) must be at least less than -85dB. This means 10 log (BW x IBN) < -85. If BW=10kHz, then IBN<-125dB/Hz. IBN includes both quantization noise and circuit noise.

As the input referred noise (IRN) of the first integrator reaches to the output of the modulator, the IRN must be less than -125dB/Hz.

I have a continuous time (CT) third order modulator that produces SNDR=98dB when the circuit noise is not considered in the a transient simulation. When I use transient analysis with transient noise in Cadence-spectre, the SNR drops to 60dB. Replacing the circuits with VerilogA modules showed the noise is due to the Active-RC integrator. However, small signal noise analysis of the integrator shows IRN < -140dB/Hz.

I wonder if the transient noise analysis is producing correct results.
Please let me know your ideas.
Thank you,
Ali

Title: Re: noise in delta sigma modulator design
Post by Alexandar on Apr 8^th, 2011, 4:49am

Did u make a hand calculation of your expected circuit noise?

Title: Re: noise in delta sigma modulator design
Post by naderi on Apr 8^th, 2011, 6:33am

The intended technology offers the noise data by some graphs for 3 transistor sizes. Scaling the graphs for transistors in the design then reading the data from those curves makes the the hand calculation highly error prone. My trials didn't match to either transient or noise analysis results.

Do you think that the maximum step size in transient analysis may effect on the amount of injected noise?

Regards,
Ali

Title: Re: noise in delta sigma modulator design
Post by Alexandar on Apr 12^th, 2011, 5:29am

Well I find transient noise simulation tricky to use. In my experience it costed too much time to get some reasonable results out of it.
So that is why I advise more hand calculation. You should obtain some simple formula depending on capacitances only, whatever MOS devices u use. (kTC noise)

Title: Re: noise in delta sigma modulator design
Post by naderi on Apr 12^th, 2011, 6:08am

Not always possible. For example, when you design a continuous time amplifier, its noise depends on gm and transistor size of its input stage. There is no cap to integrate the noise.

I think the noise analysis is based on behavioral models and is not a good match with transient noise analysis, which is based on probability models.

It seems other experience designers do not trust on either of them and consider 50% more noise than the worse results. I wonder this may lead to over design.

Anyway, I found during a few trials that coefficient scaling can magically alleviate the output noise (what ever source it may have). It could restore more than 20dB of the output SNR in my case.

Ali