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Modeling >> Behavioral Models >> SINC verilog-A modeling
https://designers-guide.org/forum/YaBB.pl?num=1302272529

Message started by usr on Apr 8^th, 2011, 7:22am

Title: SINC verilog-A modeling
Post by usr on Apr 8^th, 2011, 7:22am

Hi,

I am trying to build SINC function to represent integrate and dump behavior. I used bilt-in verilog-A idt() function to integrate but it seems I cannot get good enough accuracy.
To verify my results I use Cadence Spectre.
Has anyone coded SINC function before?

Thanks.