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Design Languages >> Verilog-AMS >> verilog-AMS update issue
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Message started by eecs4ever on Apr 14^th, 2011, 11:33pm

Title: verilog-AMS update issue
Post by eecs4ever on Apr 14^th, 2011, 11:33pm

Hi,

I've found that when I run AMS simulations, it does not updated properly.

For example. In my verilog file, i have a parameter which defines the period of a clock signal to be 100ns. If i change this parameter to 50 ns and save the verilog file. And then netlist & run. The simulation still generates a clock signal at 100 nS even though i've updated this parameter to other values!

.parameter clockperiod = 100n // 50n , 25n , 200n

However, if i hardcode the number into the clock generating expression.

For example

always #(25n) clk = ~clk;

then the clock period will update to reflect the 50ns period.

Does any one know why AMS does not update the parameter properly?

Thanks :)

Title: Re: verilog-AMS update issue
Post by Marq Kole on Apr 15^th, 2011, 12:58am

Hi,

You will need to provide more information:
- what AMS tools do you use, i.e. Cadence tools, Synopsys tools, etc.
- how do you control your simulation, i.e. from a script or through a GUI?
- what is the relation between the parameter in your verilog-file (which I presume has a format parameter integer clockperiod = 50) and the .parameter line you showed?

Cheers,
Marq