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Design Languages >> Verilog-AMS >> How could I make the Bits as a variable or param in verilogA?
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Message started by newic on Apr 23^rd, 2011, 5:21am

Title: How could I make the Bits as a variable or param in verilogA?
Post by newic on Apr 23^rd, 2011, 5:21am

How could I make the Bits as a variable or param?

`include "constants.vams"
`include "disciplines.vams"

`define Bits 8

module adc (out, in, clk);
....
....
endmodule

Title: Re: How could I make the Bits as a variable or param in verilogA?
Post by Geoffrey_Coram on Apr 25^th, 2011, 5:59am

In principle, you could use a parameter (but NOT a variable); see this example:

http://www.designers-guide.org/VerilogAMS/functional-blocks/data-converter/converter-lrm.vams

module adc (out, in, clk);
parameter integer bits = 8 from [1:24]; // resolution (bits)
...
input in, clk;
output [bits-1:0] out;

However, I'm not aware of any simulator that supports this; they all need the number of terminals of the adc to be known before parameter processing.