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Design Languages >> Verilog-AMS >> How to implement multiple assignment in the case statements?
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Message started by newic on May 4^th, 2011, 7:15pm

Title: How to implement multiple assignment in the case statements?
Post by newic on May 4^th, 2011, 7:15pm

How to implement multiple assignments in the case statement (as like LUT)?
there is a syntax error for multiple assignments.

the 'code' range from 0-3 for a simplified version (2bit)

case(code)
0: c1=0, c0=0;
1: c1=0, c0=1;
2: c1=1, c0=0;
3: c1=1, c0=1;
default: c1=0, c0=0;
endcase

Title: Re: How to implement multiple assignment in the case statements?
Post by Ken Kundert on May 5^th, 2011, 12:11am

Put them in a begin/end block.

-Ken

Title: Re: How to implement multiple assignment in the case statements?
Post by newic on May 5^th, 2011, 6:25am

you're right :)