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Design Languages >> Verilog-AMS >> Verilog-AMS always @(above issue
https://designers-guide.org/forum/YaBB.pl?num=1304611255

Message started by Sumit Adhikari on May 5^th, 2011, 9:00am

Title: Verilog-AMS always @(above issue
Post by Sumit Adhikari on May 5^th, 2011, 9:00am

Hello All,

I have a piece of code like as follows :

real osc_out_val ;
real osc_out_r ;
analog
begin//{
osc_out_val = V(osc_out);

if(osc_out_val >= 0.6) osc_out_r = 1.0 ;
else osc_out_r = 0.0 ;

end//}

logic out ;
reg out ;
always @(above(osc_out_val - 0.6)) out = 1'b1 ;
always @(above(0.6 - osc_out_val)) out = 1'b0 ;

The problem is "osc_out_r" is correctly changing but "out" seldom changes and is glitchy.

What could be the issue ?

By the way I do not have a converging dc solution and the message from ultrasim is as follows :

**** NUM_EVENTS: 159894 ****

WARNING (USIM-6501): The DC solution did not converge at ''dc_maxevent''.
The UltraSim simulator will approximate the DC solution. Try using a
different dc option to improve DC accuracy.
WARNING (USIM-6502): The DC simulation ended prematurely and the results
may be incorrect. Try using a different dc option to improve DC
accuracy before running the simulation again.

DC: user time: 0:10:20 (620.350 sec), system time: 0:00:04 (4.560 sec), real time: 0:10:26 (626.300 sec)
DC: memory: 83.8369 MB total: 107.0373 MB

Regards,
Sumit

Regards,
Sumit

Title: Re: Verilog-AMS always @(above issue
Post by Geoffrey_Coram on May 6^th, 2011, 7:45am

I thought @above was an analog event -- ie, it should go in the analog block. It is supposed to control the analog timestep to accurately resolve the crossing, but you've got it in a digital always block.

Title: Re: Verilog-AMS always @(above issue
Post by Sumit Adhikari on May 6^th, 2011, 8:40am

Yes, but in that case "out" cannot be a logic type!

Title: Re: Verilog-AMS always @(above issue
Post by boe on May 6^th, 2011, 11:30am

Sumit Adhikari,
try using an integer in the analog block; then use a digital always block to test the integer and convert it to logic.

B O E

Title: Re: Verilog-AMS always @(above issue
Post by Sumit Adhikari on May 9^th, 2011, 1:22am

Thanks,

I tried it earlier. but the integer has been declared in the analog block and affirma does not compile the digital check over the integer. Following is the code for your reference :

real osc_out_val ;
real osc_out_r ;
logic out ;
reg out ;
integer flag ;
analog
begin//{
osc_out_val = V(osc_out);

if(osc_out_val >= 0.6) osc_out_r = 1.0 ;
else osc_out_r = 0.0 ;

//@(cross (osc_out_r - 0.5, 1)) $write("%2.20f,%f\n",$abstime,osc_out_r);
//@(cross (osc_out_r - 0.5,-1)) $write("%2.20f,%f\n",$abstime,osc_out_r);

@(cross (osc_out_r - 0.5, 1)) flag = 0;
@(cross (osc_out_r - 0.5,-1)) flag = 1;

end//}

//always @(above(osc_out_val - 0.6)) out = 1'b1 ;
//always @(above(0.6 - osc_out_val)) out = 1'b0 ;

//always @(cross (osc_out_r - 0.5, 1)) out = 1'b1 ;
//always @(cross (osc_out_r - 0.5,-1)) out = 1'b0 ;

always @(flag)
if(flag == 0) out = 1'b1 ;
else out = 1'b0 ;

kind of tragedy for me now! :(

Regards,
Sumit

Title: Re: Verilog-AMS always @(above issue
Post by boe on May 9^th, 2011, 9:16am

Sumit Adhikari,

Code:

input in, clk;
output out;
wire in;
reg out;
electrical clk;
always @(cross(V(clk) - 2.5, 1)) // Code to detect the analog event.
out = in;
end

should work (example code from Cadence). Alternatively (also after a Cadence example), for your example
Code:

always begin
#5 out = !flag
end

in the digital part of your module should work as well.
NB: The delay was part of the example. It should also work without.

B O E

Title: Re: Verilog-AMS always @(above issue
Post by boe on May 9^th, 2011, 9:29am

Sumit Adhikari,

Sumit Adhikari wrote on May 9^th, 2011, 1:22am:

...
osc_out_val = V(osc_out);

if(osc_out_val >= 0.6) osc_out_r = 1.0 ;
else osc_out_r = 0.0 ;

//@(cross (osc_out_r - 0.5, 1)) $write("%2.20f,%f\n",$abstime,osc_out_r);
//@(cross (osc_out_r - 0.5,-1)) $write("%2.20f,%f\n",$abstime,osc_out_r);

@(cross (osc_out_r - 0.5, 1)) flag = 0;
@(cross (osc_out_r - 0.5,-1)) flag = 1;
...

IMO, the problem with your code is that osc_out_r is discontinuous and therefore does not have any zero crossings. You should try cross directly on V(osc_out) [or on osc_out_val].
B O E

[edit]I recommend:
Code:

always @(cross (V(osc_out)-0.5, 1)) out = 1'b1 ;
always @(cross (V(osc_out)-0.5,-1)) out = 1'b0 ;

in the discrete context or similar with above. Should work.[/edit]

Title: Re: Verilog-AMS always @(above issue
Post by boe on May 9^th, 2011, 9:39am

Geoffrey,

Geoffrey_Coram wrote on May 6^th, 2011, 7:45am:

You can use @cross/@above in the digital part (discrete context) of V-AMS models to detect continuous events in the digital domain.

B O E

Title: Re: Verilog-AMS always @(above issue
Post by Sumit Adhikari on May 13^th, 2011, 1:41pm

Thanks, but this always@ stuff is not working with cadence. And this is problem is with cadence only. I checked this works with other simulator.
My old code is fine with other simulator and is a problem with cadence.

Thanks for the support.
Regards,
Sumit

Title: Re: Verilog-AMS always @(above issue
Post by boe on May 17^th, 2011, 9:08am

Sumit Adhikari,

The connect module (from Cadence) that converts analog signals into digital ones uses (excerpt):

Code:

reg Xin; real Kin;
analog Kin = ...;
always @(above(Kin-vthi,ttol,vtol)) Xin=0;
...
always @(posedge(Xin)) ...

I can assure you, it works.

Which version do you use? And which analog solver?
B O E