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Design Languages >> Verilog-AMS >> verilogA digital code shifter
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Message started by newic on May 7^th, 2011, 8:38am

Title: verilogA digital code shifter
Post by newic on May 7^th, 2011, 8:38am

try to model a digital code shifter in verilogA. It got syntax error.
"result[0:<<--? 7] = {1 0 0 1 1 1 0 1};"

Looks like I could not define the content of the array.

integer result[0:7] ;

analog begin
@( initial_step) begin
result[0:7] = {1, 0, 0, 1, 1, 1, 0, 1};
end

@( cross( V(clk)-vth, 1)) begin
temp = result[i];
i = i + 1;
if( i >=8)
i=0;
end

Title: Re: verilogA digital code shifter
Post by rfidea on May 8^th, 2011, 11:10pm

I'm not sure that you can set the value of all elements in results[0:7] as you try to do. Sometimes verilogA is limited in this kind of operations. You can try something like results[0] = 1; results[1] = 0; ...

It is not beatiful but I think it will work...

Title: Re: verilogA digital code shifter
Post by newic on May 8^th, 2011, 11:31pm

I am aware of doing that. Is there a better way?
Because i need to create a long patterns for different cases.

That shift register is to do a simple test case only

Title: Re: verilogA digital code shifter
Post by boe on May 9^th, 2011, 10:29am

Newic,

According to Cadence V-A Language reference (Sept 2010) you can use `{} to initialize parameter/localparam arrays. However, I don't know if that works elsewhere.

B O E

PS: Did you try result = ....?

Title: Re: verilogA digital code shifter
Post by newic on May 20^th, 2011, 5:56pm

seems like i got to assign the bit one by one.

Title: Re: verilogA digital code shifter
Post by Geoffrey_Coram on May 23^rd, 2011, 10:43am

Following boe's tip, perhaps you could:

`define MYMAX 7
localparam integer startval[`MYMAX:0] = `{1, 0, 0, 1, 1, 1, 0, 1};

integer result[`MYMAX:0] ;
integer k;

@(initial_step) begin
for (k=0; k<=`MYMAX; k=k+1) result[k] = startval[k];
end