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Simulators >> Circuit Simulators >> strange error when using Verilog-A blocks
https://designers-guide.org/forum/YaBB.pl?num=1304895452

Message started by dxt78 on May 8^th, 2011, 3:57pm

Title: strange error when using Verilog-A blocks
Post by dxt78 on May 8^th, 2011, 3:57pm

I'm getting a strange error when using two Verilog-A blocks (pic attached) together. I test each block on their own and they work fine. When I try to use them together though, I get this error:

"ERROR (CMI-2116): I3: Too few terminals given (3 < 4)"

The first block ("min_block") takes three voltages and finds the minimum.

The second block ("subtract_block") takes two voltages and outputs the difference.

My Verilog-A for the min_block is:

"`include "constants.vams"
`include "disciplines.vams"

module min_block(x, y, z, out);
electrical x, y, z, out;

analog begin : themodule
real vx,vy,vz;
real temp, temp2;
vx = V(x);
vy = V(y);
vz = V(z);

temp = min(vx,vy);
temp2 = min(temp,vz);
V(out) <+ temp2;
end
endmodule"

And my code for the subtract_block is:

`include "constants.vams"
`include "disciplines.vams"

module min_block(x, y, difference);
electrical x, y, difference;

analog begin : themodule
real vx,vy;
real temp;
vx = V(x);
vy = V(y);

temp = (vx - vy);
V(difference) <+ temp;
end
endmodule

Title: Re: strange error when using Verilog-A blocks
Post by dxt78 on May 8^th, 2011, 4:13pm

Edit: ok sorry I actually found the problem. I created the 2nd block, from the first, but forgot to change the module name!