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https://designers-guide.org/forum/YaBB.pl Design >> Analog Design >> Native vs Standard Vt or Low Vt NMOS https://designers-guide.org/forum/YaBB.pl?num=1305114536 Message started by hacksgen on May 11th, 2011, 4:48am |
Title: Native vs Standard Vt or Low Vt NMOS Post by hacksgen on May 11th, 2011, 4:48am Hi everyone, As I understand the native devices have lowest threshold close to zero, better matching and also low noise like flicker due to low doping. Why is it that then not many designs use them for design of analog circuits like opamps in advanced tech. such as 65nm or 90nm where we have low voltage headroom?. I have searched online and read through many documents but none of them clarify why native is not preferred over standard or low Vt? Can anyone explain this perhaps in relation to an opamp as an example. Many Thanks |
Title: Re: Native vs Standard Vt or Low Vt NMOS Post by Alexandar on May 11th, 2011, 5:37am Come on.. did u really think about it? Let me give u some questions. And see if u can answer them.. - Do native transistors come for free? Or do u need an extra mask? - How is the matching and modelling of native transistors? - How usefull is a native transistor? For example in your opamp, can u easily build a current mirror with native transistors? |
Title: Re: Native vs Standard Vt or Low Vt NMOS Post by hacksgen on May 11th, 2011, 6:56am Hi Alexander, Like I said, my understanding comes from what I read in other forums and few papers found on IEEE. So it might be that I am wrong which is why I post my question here. Usually there is no need of additional mask in creating native transistors since it is formed directly on the substrate. (I quote this from a IEEE paper that I found). Even if an additional step is needed this should only increase the fabrication costs which I am not concerned with here. I am more interested in its use for building analog blocks assuming costs are not a factor. Matching relates to how the transistors are uniform in there properties and I think the uniform doping of the substrate allows only small variations between transistor parameters like in case of a curent mirror. I dont understand what you mean by modelling. Do you mean the model parameters provided by the foundry? From the lecture material provided in the website of Prof. Philip E. Allen it is given that native transistors allow increased ICMR in an opamp when characterized. Did you mean this that the transistors are not characterized properly? The usefulness of the native transistor is something I am not sure about since I have not found many papers using it. This is why I put of the question here so experienced forumites might answer. As I have never used it or created layouts from it so haven't got a clue as to whether creating layouts is hard or easy. |
Title: Re: Native vs Standard Vt or Low Vt NMOS Post by boe on May 12th, 2011, 12:54am Hi, Let me give you a few pointers. hacksgen wrote on May 11th, 2011, 4:48am:
hacksgen wrote on May 11th, 2011, 6:56am:
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B O E |
Title: Re: Native vs Standard Vt or Low Vt NMOS Post by AnalogDE on May 12th, 2011, 9:46am I don't get what's wrong with using 0-vt (native) transistors in a current mirror configuration. In my process they have a lower mismatch coefficient. As long as I can bias them with a good enough overdrive what's the issue here? They should work better since Vth=0 leaves more headroom. |
Title: Re: Native vs Standard Vt or Low Vt NMOS Post by boe on May 12th, 2011, 10:46am AnalogDE wrote on May 12th, 2011, 9:46am:
B O E |
Title: Re: Native vs Standard Vt or Low Vt NMOS Post by AnalogDE on May 12th, 2011, 11:12am I simulated a comparator across PVT and they seemed to work fine. They are biased in saturation. |
Title: Re: Native vs Standard Vt or Low Vt NMOS Post by Alexandar on May 12th, 2011, 11:56pm PVT? Suppose your minimum Vds=200mV. So your Vgs-Vt must be higher than that. Including process and temperature... your overdrive voltage must be huge to have some reliable operation around the corners... |
Title: Re: Native vs Standard Vt or Low Vt NMOS Post by boe on May 13th, 2011, 6:22am Hi AnalogDE, Did you try minimum Vt corner? Remember Vds > Vgs - Vt requires Vt > 0 for standard current mirror topology. B O E |
Title: Re: Native vs Standard Vt or Low Vt NMOS Post by RobG on May 13th, 2011, 8:28am Sheese, you guys are being a little harsh, it was a fair question. Personally, I have never been involved with a process that had a "native" device for free even though that some claim that no extra steps are needed (all you need to do is block the implant, and not just once upon a time). This is too bad because they have some neat uses and are used all the time when available. You mostly have to make sure the gate-drain has enough breathing room. That, and they don't always turn off with Vgs=0 (so you can use them for current sources without all the crap generally required). So to answer your question, it isn't used generally available so that is why people don't use them more. (Matching is better because there are less dopants, Alexandar, and modeling isn't an issue.) Two uses that I have seen are opamps that can have rail-to-rail inputs (the VT is 0 or negative when the input is at the bottom rail, but body effect increases it enough to function when at the top rail). There was a paper (ISSCC?) a while back with this application. The other use is a "free" cascode (0-Vt on top of a normal Vt). rg |
Title: Re: Native vs Standard Vt or Low Vt NMOS Post by loose-electron on May 13th, 2011, 11:15am Some background: Threshold on CMOS can be anything you want it to be. Anything. It is selectable by the implant doping under the gate region. This is very much a foundry controlled thing. (Also affected by the dielectric of the gate oxide and thickness of the oxide) PMOS/NMOS thresholds are typically set at 25% to 35% of the voltage between Vdd and ground. Why these threshold levels? Logic Design - it gives the best logic immunity to false logic states due to ground bounce and power rail dips. So called "native" transistors, used to also be known as "depletion" transistors, where the Vth could be near zero, or even negative. (You had to hold the gate to a negative voltage on NMOS to keep the thing turned off) My experience with foundries has shown that the generic transistors that are commonly used in the digital design are the best controlled, most accurately modeled, devices, just due to foundry priority. Because of the above fact, I try to avoid using the "native" devices. Better matching? Perhaps, but they data collected needs to be questioned. |
Title: Re: Native vs Standard Vt or Low Vt NMOS Post by rfcooltools.com on May 13th, 2011, 11:57am Native devices aside from the questionable modeling usually have a minimum length several times greater than the process node. For example 40nM process has a min length of 300nM for the zero Vt devices. I find them to be useful as source followers where dc headroom is limited. http://rfcooltools.com |
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