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Design >> Analog Design >> Very Strange results ramping Vgs of stacked PMOS
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Message started by RobG on May 13^th, 2011, 3:58pm

Title: Very Strange results ramping Vgs of stacked PMOS
Post by RobG on May 13^th, 2011, 3:58pm

Check this out: I am ramping the gate-source voltage of two PMOS devices in series. The center point goes 11 volts below the supply with fast ramps if the channel length is long (25um long, 1um wide). It only dips slightly with a channel length of 5um. The magnitude of the dip is less with slower ramps.

Now, because I'm so incredibly clever, I put several in series to create a pulse train. See, a simple three bit ADC. I'm sure it isn't a modeling issue since it isn't a natural device ;).

Anyone ever see this before? I've noticed the little bump in the center of stacked devices in nand and nor gates before. I've always wondered what was happening. I've never seen anything like this before.

Any fixes? This is a real headache for me because I am building a 6v opamp in a 3V process and need to be able to flag "real" gate-source exceedences and not be chasing this stuff down. Putting a small cap (100f) across gate-source kills it, but I don't want to add unneeded components to the circuit.

[edit --- this silly IC6 plotting program doesn't match the colors on the schematic with the colors on the plot. On the second plot the curves from left to right are Vbat, a, b, ....g where a is the drain of the uppermost PMOS, b is the next one down, etc).]

Title: Re: Very Strange results ramping Vgs of stacked PMOS
Post by zwtang on May 14^th, 2011, 6:32am

Hi, RobG
There does not exist this dip phenomena in other Foudry Lib. Maybe it is modelling issue.

zwtang
2011/5/14

Title: Re: Very Strange results ramping Vgs of stacked PMOS
Post by RobG on May 14^th, 2011, 7:33am

zwtang wrote on May 14^th, 2011, 6:32am:

Hi, RobG
There does not exist this dip phenomena in other Foudry Lib. Maybe it is modelling issue.

zwtang
2011/5/14

yeah, when you generate -11 V from a 0 => 3V ramp it just might be a modeling issue ;). I'm pretty sure they are BSIM models which have issues when connected in series like I did.

Did you try it with your process? I'm wondering how easy it is to generate this error. It is much worse as channels get long. I've seen small dips before on this center node in logic gates (similar to the L=5 case), but nothing like this.

This is a 0.18u process, but I'm using the thick gate devices.

Title: Re: Very Strange results ramping Vgs of stacked PMOS
Post by nrk1 on May 14^th, 2011, 3:23pm

RobG,

Most likely this is due to quasi-static modeling. When the transistors turn on, some (positive) charge is sucked from the drain/source, dipping their potential. This takes some time, but, in quasi-static models, it is instantaneous. The time is ~ 1/omega_T of the transistor. My guess is that this is a quasi-static model and the instantaneous drain of the entire charge from node 'a' makes it dip a lot.

omega_T (gm/Cgs) = 3/2*mu*(VGS-VT)/L^2 turns out to be ~ 10^7 rad/s for L=25um (assuming mu=100cm^2/V/s, VGS-VT=1V---all rough numbers). This gives 1/omega_T ~ 100ns. For a 50ns ramp, the charge buildup is definitely not quasi-static.

The one with the series connected transistors is likely more accurate, as their omega_T is 8^2=64 times higher. I guess you can split it into more and more pieces and see when the results (at the appropriate corresponding nodes) become consistent.

Cheers
Nagendra

Title: Re: Very Strange results ramping Vgs of stacked PMOS
Post by nrk1 on May 14^th, 2011, 3:29pm

Sorry-didn't look at the second schematic carefully. What I assumed was that you cut up a 25u length transistor into four series connected L=6.25u transistors (The number in the last para should have been 4^2, not 8^2).

What you can try is to construct each L=25u transistor as a series combination of N transistors of L=25u/N (same width as the original). Increase N and see when node "a" shows consistent results. This is a way of modeling non quasi static nature of charge buildup in the channel. There is a slight problem-the "intermediate" transistors should not have the source and drain junctions, but when you use normal transistors like this, they do---but may not be such a serious issue in this case.

Nagendra

Title: Re: Very Strange results ramping Vgs of stacked PMOS
Post by RobG on May 15^th, 2011, 11:31am

Thanks nrk1, I knew nothing about that effect. That quirk would explain what I'm seeing. I found a little documentation: http://nikola.com/pdf/bsim3ch5.pdf . The models are BSIM3v3 and the documentation says they are NQS, but I do not see the NQSMOD parameter in the model file so I assume the documentation is incorrect as it appears the default is QS (true?).

Like you predicted, the effect worsens if I make the PMOS longer and goes away if I put a bunch of short channels in series. I've also since found that I get the same effect if I replace the "bottom" PMOS with a diode connected NMOS, so I'm guessing the rectifying property of the circuit prevents the charge you are talking about from going anywhere.

Is this effect real at all? I can see how Cgd could couple the voltage ramp to the drain, but can't see how any voltage amplification could take place. In addition, when I put a cap there the effect was moderated considerably.

Title: Re: Very Strange results ramping Vgs of stacked PMOS
Post by nrk1 on May 15^th, 2011, 7:27pm

Yes, I believe by default non quasi static modeling is off. Maybe interesting to simply add nqsmod=1 and see what happens. In particular, nqsmod=1 with long transistor gives the same results as nqsmod=0 and a series combination of many shorter transistors. This will also build confidence in simulation results.

> I get the same effect if I replace the "bottom" PMOS with a diode connected NMOS, ...

By "get the same effect" do you mean the same effect as cutting up the pMOS into shorter transistors, i.e. the dip reduces? Anyway, an nMOS would have the drain bulk diode from 'a' to ground which would clip a negative dip.

> but can't see how any voltage amplification could take place ...

(General possibility, not a particular analysis of this circuit) Voltage amplification can happen when caps are nonlinear and their values change. e.g. If you end up with a given charge across a cap and the cap value reduces, the voltage across it increases in the same proportion that the cap reduces. (This is the basis for parametric amplifiers). In this case you do have strong nonlinear behavior as the transistors go from off to on.

Cheers
Nagendra

Title: Re: Very Strange results ramping Vgs of stacked PMOS
Post by loose-electron on May 16^th, 2011, 5:37pm

Questions:

Same results using a DC sweep instead of a transient model?

Model type ? (BSIM ??)

Specific Foundry process (TSMC 90nm?)

Discontinuty problems existed in a big ugly way with the older transistor models.

Also, runa set of bias curves on the transistors thru the op points shown (Vgs, Id, Vds) and see if anything is seen there.

Title: Re: Very Strange results ramping Vgs of stacked PMOS
Post by RobG on May 16^th, 2011, 6:17pm

loose-electron wrote on May 16^th, 2011, 5:37pm:

No, it is a transient effect, with a faster ramp resulting in a larger jump. I think nkr1 nailed the problem.

Title: Re: Very Strange results ramping Vgs of stacked PMOS
Post by loose-electron on May 17^th, 2011, 1:06pm

fair enough, just asking the questions....

Title: Re: Very Strange results ramping Vgs of stacked PMOS
Post by Alexandar on May 18^th, 2011, 4:18am

RobG wrote on May 13^th, 2011, 3:58pm:

I'm sure it isn't a modeling issue since it isn't a natural device ;).

HAHAHAHA ;D

Title: Re: Very Strange results ramping Vgs of stacked PMOS
Post by RobG on May 18^th, 2011, 8:24am

Lex wrote on May 18^th, 2011, 4:18am:

RobG wrote on May 13^th, 2011, 3:58pm:

I'm sure it isn't a modeling issue since it isn't a natural device ;).

HAHAHAHA ;D

I'm glad someone caught that. BTW, my original comment on the natural NMOS models is related to this point: I don't trust any model no matter how much data is used to back the Vt and mobility values: a good design is insensitive to those parameters and as this post shows, there are often bigger issues with the model itself.

Title: Re: Very Strange results ramping Vgs of stacked PMOS
Post by Alexandar on May 18^th, 2011, 11:59pm

RobG wrote on May 18^th, 2011, 8:24am:

Lex wrote on May 18^th, 2011, 4:18am:

RobG wrote on May 13^th, 2011, 3:58pm:

I'm sure it isn't a modeling issue since it isn't a natural device ;).

HAHAHAHA ;D

A fair amount of skepticism is always good when u look at models, and making something by design correct is gold.

But some models are just more accurate than others. So if it's low risk, it's fine: u could use your natural devices to make sample capacitors.

And suppose your bipolar models are crappy, then how to make your bandgap reference perform well without too much spread. I mean, sure it wil start up and settle and give some voltage. But temperature behavior can be way off, with crappy models.

Title: Re: Very Strange results ramping Vgs of stacked PMOS
Post by RobG on May 19^th, 2011, 8:03am

Lex wrote on May 18^th, 2011, 11:59pm:

[quote author=RobG link=1305327527/0#11 date=1305732257]

A fair amount of skepticism is always good when u look at models, and making something by design correct is gold.

But some models are just more accurate than others. So if it's low risk, it's fine: u could use your natural devices to make sample capacitors.

And suppose your bipolar models are crappy, then how to make your bandgap reference perform well without too much spread. I mean, sure it wil start up and settle and give some voltage. But temperature behavior can be way off, with crappy models.

Alaxander, you have picked one of the few circuits that really matter, and it really has nothing to do with whether a natural device is poorly modeled compared to a normal device. Nowadays most of the problems are layout dependent, not because the nominal Vt is 50mV off. If you need a lot of history to get accurate models you have to ask yourself what is going on. Incompetent modeler? Unstable process? Are things going to be better because you are using a normal NMOS instead of a natural for a cascode or diff pair? No, those are other issues. Man up as the say, we've been designing with crappy models for decades ;D . People design across currents and device sizes that vary by orders of magnitudes. The models can't be accurate over that sort of range. On top of that, they have their inherent quirks (like above).

Anyway, as someone who made a career out of fixing other people's bandgaps I can tell you most of the time the person who created the models are blamed when it is the designer's fault. They run the diodes at too high a current density so poorly controlled effects dominate. Or the system is too sensitive to mismatches. Or they match the wrong resistors, or they decide that since it doesn't have to be "that accurate" they can cut corners only to find some effect they didn't think of creeps in. The way to deal with poorly modeled new-process bipolars in a bandgap is to add trim, and to design in a region where the model will give consistent results, and realize that the "magic voltage" magnitude may not be exactly where the simulation says it is.

That's my experience anyway,
Rob

Title: Re: Very Strange results ramping Vgs of stacked PMOS
Post by loose-electron on May 19^th, 2011, 11:39am

See my comments on models here:

http://effectiveelectrons.com/modeling.htm

Some foundries provide consistent quality, others produce consistent junk.

Title: Re: Very Strange results ramping Vgs of stacked PMOS
Post by RobG on May 19^th, 2011, 1:19pm

loose-electron wrote on May 19^th, 2011, 11:39am:

See my comments on models here:

http://effectiveelectrons.com/modeling.htm

Some foundries provide consistent quality, others produce consistent junk.

I found this article by you to be pretty good: http://effectiveelectrons.com/whitepapers/simulationvssilicon.pdf
It looks like you have been pulling out your hair over models for some time :D