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Design >> RF Design >> LNA Design
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Message started by chris2312 on May 23^rd, 2011, 9:32am

Title: LNA Design
Post by chris2312 on May 23^rd, 2011, 9:32am

Hello,

I'm new in design of integrated circuits. I have to design a lna. I choosed cascode topology to achieve high gain at high frequencies. My problem is to find a bias point with minimum noise of the transistor. I have red that most lna's operate iun class-A, so you have to choose the bias current that Ic = Icmax/2. Othwerwise the shot noise oft the transistor will increase with high current, so i choosed a bias current which is smaller than Icmax/2. I plotted gm vs. NF to find a good tradeoff first for a common emitter stage. Now I want to do the same for the cascode to find an optimum, but I have no idea how to realize it, because of the bias voltage of the load transistor. Can you give me some hints ? Thanks for response.

Title: Re: LNA Design
Post by rfcooltools.com on May 23^rd, 2011, 12:40pm

Chris2312,

The noise for the cascode stage will be degenerated by the output impedance of common emitter stage. With that said size the cascode to operate at peak ft, then check the noise contribution, if negligible then stop otherwise increase the size until the tradeoff of bandwidth and noise is acceptable.

http://rfcooltools.com

Title: Re: LNA Design
Post by vp1953 on May 24^th, 2011, 10:14am

Hi Chris 2312

I do not think LNA's operate like Class A power amps. Even before you get to zero current (due a large RF signal), there are some many issues relating to nonlinearity etc that prevent typical usage at high input power levels. There are some good examples in Tom Lee's book (most of which you can read online). Rfcooltools has provided a good summary of what needs to be done to reach noise-gain targets

Title: Re: LNA Design
Post by purplewolf on May 28^th, 2011, 2:21pm

@rfcooltools.com
can you tell whats the simulation setup in spectre to determine the peak ft. Is peak ft dependent on demensions of device or only technology?
Secondly, i think the problem with increasing the size of common gate device would compromise the noise performance much more severe than bandwidth as the output impedance mismatch between common collector and common gate of cascode provides the best decoupling between input and output by minimizing effect.
@vp1953 If LNA is operated as class-B or class-C would create lots of harmonic contents. So, i think biasing should be in class A or worst case class AB

Title: Re: LNA Design
Post by loose-electron on May 28^th, 2011, 6:03pm

RF front ends are not a good place to have learning experiences in IC design.

If it is for any typical RF front end, it is going to have to have a Class A structure to meet linearity requirements.

Do you have:
Noise spec
Linearity Spec
BW spec
Gain Spec
defined source impedance
defined output load

min max criteria on all, IP2, IP3 specs for linearity?

thats some of the very basic stuff you need before you get started.

Title: Re: LNA Design
Post by vp1953 on May 30^th, 2011, 5:54pm

Hi Purplewolf,

LNA is only in Class A, I dont think it ever operates in class A-B. Even here operation is in the small signal regime unlike power amps where it is predominantly large signal operation.

You can find some good tutorials at

http://www.odyseus.nildram.co.uk/RFIC_Circuits_Page.htm

Tom Lee's book also has some good design examples.

Title: Re: LNA Design
Post by loose-electron on May 30^th, 2011, 5:57pm

vp1953 wrote on May 30^th, 2011, 5:54pm:

Almost always Class A for linearity - Never say never!

Title: Re: LNA Design
Post by purplewolf on May 31^st, 2011, 7:30am

Thanks vp1953 and loose-electron.. i got the point

Title: Re: LNA Design
Post by rfcooltools.com on May 31^st, 2011, 12:13pm

purplewolf,

many bjt foundries provide the peak ft as a component display parameter after running a DC operating point. Additionally ft can be approximated as gm/((Cbe+Cbc)*2*pi).

http://rfcooltools.com