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Modeling >> Behavioral Models >> Trouble writing VerilogA model for a circuit block with vdd! input pin
https://designers-guide.org/forum/YaBB.pl?num=1306288839

Message started by SJ on May 24^th, 2011, 7:00pm

Title: Trouble writing VerilogA model for a circuit block with vdd! input pin
Post by SJ on May 24^th, 2011, 7:00pm

I am trying to write VerilogA behavioral models for some sub-blocks/sub circuits in our existing IC designs. One of the sub blocks has a pin vdd!. When I generate a veriloga module template using the VerilogA editor, the port appears in the port declarations and pin names as \vdd!. On my top level test schematic, I have a 3.3V supply connected that acts as vdd!. In the config view, when I set up the view to use as schematic, there is no problem and the circuit simulates fine. However when I change the view to VerilogA there is a netlister error.

ERROR: Netlister : terminal 'vdd!' of instance 'I4', in cell 'ClkGenerator', view 'schematic' : cannot be found in the switched master of the instance.

Anyone have any ideas on how to make this work?

Title: Re: Trouble writing VerilogA model for a circuit block with vdd! input pin
Post by boe on May 27^th, 2011, 10:10am

SJ,

rename the pin in the schematic.

B O E

PS: Do you know where this name comes from? And which tools do you use?