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Design Languages >> Verilog-AMS >> initial_step and final_step in dc analysis
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Message started by danmc on May 26^th, 2011, 6:19pm

Title: initial_step and final_step in dc analysis
Post by danmc on May 26^th, 2011, 6:19pm

Could anyone shed some light on how exactly initial_step and final_step in Verilog-A are executed in a dc operating point analysis? I'm wanting to load some parameters from a file before the dc analysis happens and then write out some parameters to the same file after the dc analysis happens. Seemed easy enough but I get complaints that make it sound like my $fopen, $fread, $fclose sequence in @(initial_step) didn't fully complete before the @(final_step) $fopen, $fdisplay, $fclose sequence.

Thanks in advance for any insight here.
-Dan

Title: Re: initial_step and final_step in dc analysis
Post by boe on May 27^th, 2011, 3:33am

Dan,

Which tool (and which version) do you use? What errors do you get?

B O E

Title: Re: initial_step and final_step in dc analysis
Post by danmc on May 27^th, 2011, 4:36am

simulator is spectre 7.1.1.221.isr13

The exact warnings/errors are:

Warning from spectre during DC analysis `dcOp1'.
WARNING (VLOGA-5090): "/home/dan/myLib/myvacell/veriloga/veriloga.va" 58: ITEST: Overwriting file /tmp/statefile.txt. Saving old contents of file in /tmp/myfile.txt~.

^^^ line 58 is in my @(final_step) block and says
fp = $fopen("/tmp/myfile.txt", "w");

Fatal error found by spectre during DC analysis `dcOp1'.
FATAL (VLOGA-5103): "/home/dan/myLib/myvacell/veriloga/veriloga.va" 36: ITEST: File '/tmp/myfile.txt' is already open for writing. The software is trying to open this file for reading. Close the file and try again.

^^^^ line 36 is in my @(initial_step) block and says
fp = $fopen("/tmp/myfile.txt", "r");

both my @(initial_step) and @(final_step) blocks end with $fclose(fp). What doesn't make sense to me is that it looks like opening for writing happened before opening for reading even though I thought everything in @(initial_step) should have run to completion before anything in @(final_step) began.

FATAL (VLOGA-5078): "/home/dan/myLib/myvacell/veriloga/veriloga.va" 45: ITEST: Invalid file descriptor. Correct the problem and try again.

^^^^ This is inside my @(initial_step) block shortly after opening the file. It fails because of the preceeding error (not being able to open the file). line 45 is:

$fscanf(fp, "%d", myint);

At first I suspected that I do not fully understand @(initial_step) and @(final_step) in the context of a 'dc' simulation but now I think I do not understand some fine details of file I/O because the following code shows the same problem:

Note, all I am doing is opening a file, reading some variables, closing it, then re-opening for writing and putting out some new values and closing. Is it perhaps the case that the $fopen()'s do not execute in order? That seems to go against how Verilog-A is supposed to work.

@(initial_step) begin
$display("starting initial_step");
fd = $fopen("/tmp/myfile.txt", "r");
$display("read fd = %d", fd);
$fscanf(fd, "%d", val1);
$fscanf(fd, "%d", val2);
$fscanf(fd, "%d", val3);
$display("Read val1 = %d", val1);
$display(" val2 = %d", val2);
$display(" val3 = %d", val3);
$fclose(fd);

fd = $fopen("/tmp/myfile.txt", "w");
$display("write fd = %d", fd);
$fdisplay(fd, "%d", val1+1);
$fdisplay(fd, "%d", val2+1);
$fdisplay(fd, "%d", val3+1);
$fclose(fd);
$display("finished initial_step");
end

Title: Re: initial_step and final_step in dc analysis
Post by boe on May 27^th, 2011, 9:43am

Dan,

If you use $debug instead of $display, you get the output in the log file:
... starting initial_step read fd = 2 Read val1 = 1 val2 = 2 val3 = 3 Closed 2 Warning from spectre during DC analysis `dcOp'. WARNING (VLOGA-5090): "x.va" 18: x1: Overwriting file /tmp/myfile.txt. Saving old contents of file in /tmp/myfile.txt~. write fd = 2 About to close 2 Closed 2 finished initial_step starting initial_step Fatal error found by spectre during DC analysis `dcOp'. FATAL (VLOGA-5103): "x.va" 8: x1: File '/tmp/myfile.txt' is already open for writing. The software is trying to open this file for reading. Close the file and try again. read fd = 0 Fatal error found by spectre during DC analysis `dcOp'. FATAL (VLOGA-5078): "x.va" 10: x1: Invalid file descriptor. Correct the problem and try again. Analysis `dcOp' was terminated prematurely due to an error. ...
As you can see, the initial_step block is executed twice!
However, if you write in a different file using
Code:

fd2 = $fopen("/tmp/myfile2.txt", "w");
$debug("write fd = %d", fd2);
$fdisplay(fd2, "%d", val1+1);
$fdisplay(fd2, "%d", val2+1);
$fdisplay(fd2, "%d", val3+1);
$debug("About to close %d", fd2);
$fclose(fd2);
$debug("Closed %d", fd2);

it works. I suppose you will have to ask Cadence why...

B O E
PS: spectre 7.1 is quite old, but spectre still behaves the same in version 10 (which I have used now).

Title: Re: initial_step and final_step in dc analysis
Post by Geoffrey_Coram on May 27^th, 2011, 9:46am

It can be a little tricky on the simulator's side to know what "initial_step" means, in light of how the behavioral code of the module may need to be re-executed for Newton iterations.

But in the Verilog-AMS LRM, the behavior of initial_step and final_step for dc sweeps was spelled out.

Title: Re: initial_step and final_step in dc analysis
Post by Geoffrey_Coram on May 27^th, 2011, 9:47am

Does anything change if you write
@(initial_step("dc"))
instead of just
@(initial_step)
?

Title: Re: initial_step and final_step in dc analysis
Post by boe on May 27^th, 2011, 10:03am

Geoffrey_Coram,
No. The initial_step block is still executed twice. And during the first pass through the code everything seems fine. That simulator tries to reopen the file in the second pass through the initial block causes the problem.
Cadence Verilog-A reference states that the file descriptor associates uniquely with the filename given. Is this supposed to mean you may open a file only once in your code?

B O E

Title: Re: initial_step and final_step in dc analysis
Post by danmc on May 27^th, 2011, 1:11pm

Geoff (hi! btw, ltns):

Adding the "dc" part made no difference.

boe:

my version of spectre doesn't even make it through the first time in the double call to initial_value without failing.

-Dan

Title: Re: initial_step and final_step in dc analysis
Post by Marq Kole on May 27^th, 2011, 1:44pm

I've done a little experimenting and it turns out you are not allowed to read and write to the same file in the same time step. If you use two different file descriptors you get a slightly different message back from Spectre:
FATAL (ASL-3241): "freadrw.va" 49: X1: Reopen '/tmp/myfile.txt' fail, cannot change access mode of the file.
You can use a trick to read the file in the first step and write it in the next step. With the code below the read and write of the same file does work.

Code:

if (fdr_opened && !fdw_opened) begin

$display("starting second step");

fdw = $fopen("/tmp/myfile.txt", "a");
fdw_opened = 1;

$display("write fd = %d", fdw);

$fdisplay(fdw, "%d", val1+1);
$fdisplay(fdw, "%d", val2+1);
$fdisplay(fdw, "%d", val3+1);

$fclose(fdw);

$display("finished second step");

end // if (fdr_opened ...

@(initial_step) begin

$display("starting initial_step");

fdr = $fopen("/tmp/myfile.txt", "r");
fdr_opened = 1;

$display("read fd = %d", fdr);

$fscanf(fdr, "%d", val1);
$fscanf(fdr, "%d", val2);
$fscanf(fdr, "%d", val3);

$display("Read val1 = %d", val1);
$display(" val2 = %d", val2);
$display(" val3 = %d", val3);

$fclose(fdr);

$display("finished initial_step");

end // initial_step

I presume that this (undocumented) limitation in Spectre is related to performance as multiple instances of the same module that do the writing and reading in the same time step (and even doing hundreds of DC iterations!) can seriously degrade performance.

Cheers,
Marq

Title: Re: initial_step and final_step in dc analysis
Post by danmc on May 28^th, 2011, 3:44am

This seems to be spectre version dependent. Some versions give the same fatal error as before, others don't give an error but don't execute the 2nd part (writing) code for me. Note that I'm doing a dc analysis and not transient.