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Design >> RF Design >> divider input waveform
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Message started by purplewolf on May 27^th, 2011, 3:58am

Title: divider input waveform
Post by purplewolf on May 27^th, 2011, 3:58am

I want to design a integer N CML based divider for PLL. The VCO will be designed later. The output frequncy of VCO will be around 1.5 GHz. I want to know whether the input waveform for divider simulation should be a sine wave or a square wave. I strongly beleive that the output of divider is square wave which is input to PFD but not sure about input waveform.
If it is a square wave, how to generate such wave at high frequencies without noise performance.

Title: Re: divider input waveform
Post by purplewolf on May 27^th, 2011, 8:13am

correction: without noise performance degradation

Title: Re: divider input waveform
Post by vp1953 on May 27^th, 2011, 6:21pm

Hi Purplewolf,

You are feeding the output of the VCO to the divider?If the VCO is LC tank based, then the output should be sinusoidal - it should be fine to feed this sinusoidal input to the input of the CML based divider.

Title: Re: divider input waveform
Post by loose-electron on May 28^th, 2011, 6:06pm

vp1953 wrote on May 27^th, 2011, 6:21pm:

if it is differential, and you are going to need to understand the output of the VCO a bit better.

1. It must be sinusoid if its an LC structure.
2. Divider system is going to effect noise/jitter performance in a big big way.

Title: Re: divider input waveform
Post by raja.cedt on May 29^th, 2011, 6:59pm

hi purplewolf,
i want to add some thing to above points.
1. As far i know for for an cml divider if you give sufficient swing it's fine, for mosfet based divider you should have min swing is 1.414*Vov and for a bjt based structure 3 to 4 VT.
2.is vco signal is getting buffered by some level converter, because this is going to add jitter (because this is the general case for any vco which has provision for testing.)?

Thanks.

Title: Re: divider input waveform
Post by purplewolf on May 30^th, 2011, 2:10am

I have not yet designed VCO but I have seen in a document on sigma delta PLL with ring oscillator , that the output is buffered with 2-3 stage differential amplifier to transform it from small swing differential to cmos rail 2 rail and it is then fed as a clock signal to sigma delta modulator.
For my case i am designing integer N PLL. I just wonder why not give the divider rectangular signal by using the approach of inverters. Because, after all the output of divider is square waveform. And also, the divider is a sort of 'digital' circuit with synchronous, asynchrous parts and counters. I still dont get why we need to feed it with sine wave just because VCO is LC tank based or what?

Title: Re: divider input waveform
Post by raja.cedt on May 30^th, 2011, 2:40am

hi,
but in your first post you said you are ging to design CML divider, now you are saying that it is simple digital circuit.

Thanks.

Title: Re: divider input waveform
Post by purplewolf on May 30^th, 2011, 2:53am

i am just calling CML divider a sort of digital circuit. i take back my words :P

Title: Re: divider input waveform
Post by raja.cedt on May 30^th, 2011, 9:20am

No man..be clear. CML is completely different than cmos. So your divider is digital one so then whats he question of wave shape. You should use square wave by buffering VCO through some level converter.

Thanks.

Title: Re: divider input waveform
Post by purplewolf on May 30^th, 2011, 10:17am

It is CML based divider. To be mor precise it is a dual modulus 8/9 prescaler using CML logic. i hope its clear now

Title: Re: divider input waveform
Post by vp1953 on May 30^th, 2011, 5:52pm

Hi Purplewolf,

For dual modulus 8/9 prescaler that uses CML, input is sinusoidal and output can also be sinusoidal. You can of course convert the output of the VCO to a square wave to feed to the divider, but at much higher power consumption - why would you want to do this?

If you search around for some papers, you should find entire schematics for aCML 2/3 or 4/5 dual modulus prescalers, which can easily be extended to 8/9

Title: Re: divider input waveform
Post by loose-electron on Jun 7^th, 2011, 5:35pm

raja.cedt wrote on May 30^th, 2011, 9:20am:

Be gentle.....
;)

Title: Re: divider input waveform
Post by wave on Jun 7^th, 2011, 6:57pm

It sounds like a classical case of a digital guy talking to an analog guy, and neither understands the other.

First, if you have 1.5G, you'll probably need a special CML or buffer to get to CML for a couple divisions. This will start as a sinusoid and be square after a divider or 2. You need to define what frequency this is at.

Now, I'm not sure it makes sense (power wise) to continue dividing 8 or 9 times in CML. While you could stay in CML --- you might be better off converting CML to CMOS, where you can run standard cells and RTL flow.

So again, I think the VCO and CML designer needs to step up first and give a spec as to what is getting divided at which frequency.
Ditto with the Refclk and input divider.

Wave
:D

Title: Re: divider input waveform
Post by purplewolf on Jul 14^th, 2011, 3:18am

I want to know whether the duty cycle of the output waveform of the divider, which is input to phase frequency detector, need to be 50%. Is there any effect on loop performance if its not 50% although the period of output frequency is correct

Title: Re: divider input waveform
Post by vp1953 on Jul 18^th, 2011, 6:59pm

Hi Purplewolf,

For phase frequency detectors, generally they are edge triggered either positive or negative, so duty cycle is not important here.

For a pure phase detector (as in an XOR gate), duty cycle is very important.