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Design >> Mixed-Signal Design >> divider jitter
https://designers-guide.org/forum/YaBB.pl?num=1306871287

Message started by smarty on May 31^st, 2011, 12:48pm

Title: divider jitter
Post by smarty on May 31^st, 2011, 12:48pm

Hi All,
I was doing jitter simulation of divider, whose input is the vco clock. This divider is part of the clock network. The network contains few gates before the divider and the output of divider is another set of gates.
When I did run jitter analysis with supply noise, I see that coming out of divider the jitter has doubled.
Jdiv2 = 2*Jin. I am unable to figure out why the jitter should be doubled.
Any suggestion would help in

Thanks,
smarty