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Design >> Mixed-Signal Design >> PLL BW correlation
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Message started by raja.cedt on Jun 1st, 2011, 2:59am

Title: PLL BW correlation
Post by raja.cedt on Jun 1st, 2011, 2:59am

I am designing a PLL for for DDR-3 purpose. Target frequency was 1.6G. Through behavior simulations i adjusted LBW 4Meg. But could you please tell me is there any way to correlate bandwidth with transient simulations. I tried many ways like finding settling time of the control voltage or o/p frequency to some %ge of PPM, but unable to correlate.


finally does any one in industry do this?

Thanks.

Title: Re: PLL BW correlation
Post by loose-electron on Jun 4th, 2011, 1:56pm

After you have the gain factors for all the PLL parts, you can do the basic math of the 2nd order control system model. From there - the voltage characterisitics on the loop filter is the next way to get things like the loop BW.



Title: Re: PLL BW correlation
Post by lwjee on Jun 4th, 2011, 10:50pm

"Design of CMOS Adaptive-Bandwidth PLL/DLLs:
A General Approach" may tell you something.

Title: Re: PLL BW correlation
Post by raja.cedt on Jun 4th, 2011, 11:16pm

hi loose elctron,
thanks for reply, after ding that math only i have started implementation, but now i want to correlate that with transient sim.

Thanks.

Title: Re: PLL BW correlation
Post by casual on Jun 6th, 2011, 8:12am

you could extract wn & damping factor. after that you could get the BW by calculation.

or else you could use pll pull-in process to estimate the BW in transient simulation.

Title: Re: PLL BW correlation
Post by loose-electron on Jun 7th, 2011, 5:42pm

Time domain responses of the voltage at the filter will show both zeta (damping) and Wo (loop bw)

Get the simulation in steady state mode, and then apply a phase or frequency step to the input and watch the charge pump and phase detector do their thing.

You may want to develop behavioral modesl of the whole loop, it speeds the simulation process up.

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