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https://designers-guide.org/forum/YaBB.pl Simulators >> Circuit Simulators >> PLL transient noise in BDAsim runtime https://designers-guide.org/forum/YaBB.pl?num=1307560865 Message started by raja.cedt on Jun 8th, 2011, 12:21pm |
Title: PLL transient noise in BDAsim runtime Post by raja.cedt on Jun 8th, 2011, 12:21pm hello all, is any one running BDAsim pll closed loop transient noise simulations. I have gone through BDA documents and ran for a PLL for closed loop. But it is taking so much of time which is very strongly depends on the lower frequency offset from the carrier . total time=tstab+(40/min offset frequency from carrier) means with 1meg offset frequency and 2u sec time for stabilization total time would be 42us, which is very long i guess and impossible for some cases.. can any one please correct if any thing wrong here. Thanks. |
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