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Modeling >> Behavioral Models >> concatenate operation
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Message started by samy on Jun 16^th, 2011, 7:19pm

Title: concatenate operation
Post by samy on Jun 16^th, 2011, 7:19pm

dear all,
i want to concatenate a register(of dynamic size as for concatenation)
with n no:of zeros where n is a generic integer number.

say for eg
num1_reg := "00" & num1;--here only two zeros are only used

i would like to make it something that would work like this

num1_reg := "N zeros" & num1;--wherein n is a generic number

how to make it work..please advice...
thanks in advance

Title: Re: concatenate operation
Post by boe on Jun 17^th, 2011, 1:51am

Samy,

Which language do you use?

B O E

Title: Re: concatenate operation
Post by samy on Jun 17^th, 2011, 2:19am

VHDL only not verilog

Title: Re: concatenate operation
Post by boe on Jun 17^th, 2011, 7:36am

Samy,

you could e.g. define a constant zero vector of sufficient size and use an N bit wide sub-vector.

B O E

Title: Re: concatenate operation
Post by samy on Jun 17^th, 2011, 9:12am

thanks boe.tat was of gr8 help

actually tat was not i was lookin for.the type-subtype wont help me b'coz the size of the main type cant be determined unless the n(for the zero's or for the main pgm) is assigned,moreover as you said the a large size for the vector is also not adviced i suppose!!