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Design >> Analog Design >> loop gain and stability for an LDO
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Message started by dxt78 on Jun 20th, 2011, 9:46pm

Title: loop gain and stability for an LDO
Post by dxt78 on Jun 20th, 2011, 9:46pm

I'm having trouble with a low dropout regulator.  I am trying to analyze its stability by breaking the feedback loop, injecting an ac signal, and analyzing the transfer function (tf=output/ac input).  But, the loop gain I get is always below 1.  Any suggestions?  Thanks very much.

Title: Re: loop gain and stability for an LDO
Post by raja.cedt on Jun 20th, 2011, 10:56pm

hi,
is this regulator? show me the clear picture...

Tx

Title: Re: loop gain and stability for an LDO
Post by buddypoor on Jun 21st, 2011, 1:16am

It's not so easy. Simply breaking (opening) the loop is not correct because the circuit looses its operating point. You must study some methods to simulate the loop gain correctly.
One simple and robust method (not 100% correct): Insert an ac source in series with the opamp output and display gain and phase for
the expression db(V(x)/V(y)).   Nodes X and y, respectively, are the nodes to the right and to the left from the ac source.

Title: Re: loop gain and stability for an LDO
Post by dxt78 on Jun 21st, 2011, 10:59am

Thanks for your feedback and help.  I'll try looking at the operating point more closely, and see if I can get things right.

Title: Re: loop gain and stability for an LDO
Post by loose-electron on Jun 21st, 2011, 4:52pm

getting proper stability in an LDO control loop is a bit messy - the output power pass transistor wiill change about 30dB in gain over the full operating range (triode to saturation) the ESR of the loading capacitor affects pole placement. Its not impossible, but it needs to be carefully examined for stability/gain/phase over all operating situations so you don't build an oscillator.


Title: Re: loop gain and stability for an LDO
Post by RobG on Jun 24th, 2011, 2:45pm

You have a pretty strange circuit there - the feedback path seems to be through the power supply of the amplifier, but there is nothing that would establish the DC operating points even if the amp output was connected to the gate of the PMOS.

In addition, I doubt if you want that PMOS bulk tied to gnd.

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