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Design Languages >> Verilog-AMS >> Writing Capacitance model with charge conservation principle
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Message started by kumar on Jun 27^th, 2011, 5:08am

Title: Writing Capacitance model with charge conservation principle
Post by kumar on Jun 27^th, 2011, 5:08am

Hi,
I would like to develop a capacitance model with charge conservation principle as explained in Ken Kundert's book. My capacitance (for pMOS) is as follows

$discontinuity(0);
if (v_GS >= vth) //cut-off region
begin
C_GS = C_sov;
C_GD = C_dov;
end
else if ((v_DS) > v_GS-vth) // linear region
begin
C_GS = C_ch/2 + C_sov;
C_GD = C_ch/2 +C_dov;
end
else // saturation region
begin
C_GS = (2/3)*C_ch + C_sov;
C_GD = C_ch/3+C_dov;
end

Now how can I calculate the total charge Q_GD, Q_GS and the corresponding curent.

I tried the following but the model doesn't converge in cadence.
Q_GD = C_GD*v_GD;
Q_GS = C_GS*v_GS;

I(g,d) <+ ddt(Q_GD);
I(g,s) <+ ddt(Q_GS);

Title: Re: Writing Capacitance model with charge conservation principle
Post by Geoffrey_Coram on Jun 27^th, 2011, 9:14am

I think you completely missed the point that was explained in Ken's book.

You need to write Q in each region, not C.

Also, Q needs to be continuous across the boundaries (check the linear region equations at v_GS == vth, you should get the same answer as cut-off).

I also think you have linear and saturation confused (or your inequality reversed); large v_DS should put the transistor in saturation.

Title: Re: Writing Capacitance model with charge conservation principle
Post by Ramkumar on Jun 28^th, 2011, 2:12am

Hi Coram,
The equations are for a pMOS. I have added the discontinuity statement in the code to take care of the discontinuities. I tried the following code with charge in each if-clause. Even then the simulator didnt converge.

$discontinuity(0);
if (v_GS >= vth) //cut-off region
begin
Q_GS = C_sov*v_GS;
Q_GD = C_dov*v_DS;

end
else if ((v_DS) > v_GS-vth) // linear region
begin
Q_GS = (C_ch/2)*(v_GS-vth) + C_sov*vth;
Q_GD = C_ch/2*(v_GS-vth)+C_dov*(v_DS-(v_GS-vth)) ;
end
else // saturation region
begin
Q_GS = (2/3)*C_ch*(v_GS-vth) + C_sov*vth;
Q_GD = (C_ch/3)*(v_GS-vth)+C_dov*(v_DS-(v_GS-vth));
end

I was able to make the equations continuous for v_GS==vth but cudn't succeed for the case v_DS = v_GS-vth. However I believe the discontinuity statement should take care of this.

Title: Re: Writing Capacitance model with charge conservation principle
Post by boe on Jun 28^th, 2011, 11:28am

Hi,
kumar.g wrote on Jun 28^th, 2011, 2:12am:

I was able to make the equations continuous for v_GS==vth but cudn't succeed for the case v_DS = v_GS-vth. However I believe the discontinuity statement should take care of this.

You use the derivative of q as current. Therefore, when q jumps the current must be infinite (or you loose charge).
Also, due to numerical errors your solution might jump several times to and fro during one crossing from linear region to saturation (or back).
Thus, it is not surprising if you get errors at this point.
B O E
PS: A real MOS transistor will change smoothly between the states.

Title: Re: Writing Capacitance model with charge conservation principle
Post by Ramkumar on Jul 1^st, 2011, 6:14am

if (v_GS >= vth) //cut-off region
begin
Q_GS = C_sov*v_GS;
Q_GD = C_dov*v_DS;

end
else if ((v_DS) > v_GS-vth) // linear region
begin
Q_GS = (C_ch/2)*(v_GS-vth) + C_sov*vth;
Q_GD = C_ch/2*(v_GS-vth)+C_dov*(v_DS-(v_GS-vth)) ;
end
else // saturation region
begin
Q_GS = (1/2)*C_ch*(v_GS-vth) + C_sov*vth;
Q_GD = (C_ch/2)*(v_GS-vth)+C_dov*(v_DS-(v_GS-vth));
end

I tried with this set of eqns. You will see that the equation holds good for v_GS==vth and v_DS==v_GS-vth. Inspite of the eqns being continuous it doesn't converge.

Title: Re: Writing Capacitance model with charge conservation principle
Post by boe on Jul 4^th, 2011, 4:21am

kumar.g wrote on Jul 1^st, 2011, 6:14am:

... Inspite of the eqns being continuous it doesn't converge.

Can you be more specific? Do you simulate only the cap? Where do you get the convergence failure (is it initial condition, what are the voltages, ...)? Simulator, settings, useful error messages...?
B O E

Title: Re: Writing Capacitance model with charge conservation principle
Post by Ramkumar on Jul 6^th, 2011, 12:49pm

Simulating `input.scs' on voelligbaf at 9:21:24 PM, Wed Jul 6, 2011 (process id: 4643).
Command line:
\
/cad/cds03/Cadence_Tools/MMSIM711_2010/tools/spectre/bin/32bit/spectre \
-env artist5.1.0 +escchars +log ../psf/spectre.out +inter=mpsc \
+mpssession=spectre3_13629_391 -format sst2 -raw ../psf \
+lqtimeout 900 -maxw 5 -maxn 5 input.scs
spectre pid = 4643

Loading /cad/cds03/Cadence_Tools/MMSIM711_2010/tools.lnx86/cmi/lib/5.0/libinfineon_sh.so ...
Loading /cad/cds03/Cadence_Tools/MMSIM711_2010/tools.lnx86/cmi/lib/5.0/libphilips_sh.so ...
Loading /cad/cds03/Cadence_Tools/MMSIM711_2010/tools.lnx86/cmi/lib/5.0/libsparam_sh.so ...
Loading /cad/cds03/Cadence_Tools/MMSIM711_2010/tools.lnx86/cmi/lib/5.0/libstmodels_sh.so ...
Auto-loading AHDL component.
Finished loading AHDL component in 0 s (elapsed).
Installed AHDL simulation interface.
Opening directory input.ahdlSimDB/ (775)
Opening directory input.ahdlSimDB/1984_umc_90_printed_el_otft_mod3_veriloga_veriloga.va.otft_mod3.ahdlcmi/ (775)
Opening directory input.ahdlSimDB/1984_umc_90_printed_el_otft_mod3_veriloga_veriloga.va.otft_mod3.ahdlcmi/Linux2.6.38.3IES+gcc/ (775)
Compiling ahdlcmi module library.
Finished compilation in 2 s (elapsed).
Installed compiled interface for otft_mod3.

Circuit inventory:
nodes 7
otft_mod3 8
quantity 9
vsource 3

Time for parsing: CPU = 344.022 ms, elapsed = 1.85556 s.
Time accumulated: CPU = 364.022 ms, elapsed = 1.85679 s.
Peak virtual memory used = 565 Mbytes.

Entering remote command mode using MPSC service (spectre, ipi, v0.0, spectre3_13629_391, ).

*************************************************
Transient Analysis `tran': time = (0 s -> 100 us)
*************************************************
Important parameter values:
start = 0 s
outputstart = 0 s
stop = 100 us

--------------------------------------------------------------------------

I have some more eqns for the static behaviour. Those r basic MOSFET eqns from any book. I dont think the problem comes from those eqns.

I have attached the schematic with this. The circuit converges when i connect a 900 Megaohm resistor from nett1 to GND

Title: Re: Writing Capacitance model with charge conservation principle
Post by Ramkumar on Jul 7^th, 2011, 12:29am

Sorry, I forgot to add the complete log file.

Title: Re: Writing Capacitance model with charge conservation principle
Post by Ken Kundert on Jul 7^th, 2011, 1:13pm

Quote:

Error found by spectre at time = 43.4433 ns during transient analysis `tran'.
ERROR (SPECTRE-16192): No convergence achieved with the minimum time step specified. Last acceptable solution computed at 43.4433 ns.

That is a pretty clear indication that the model is discontinuous. I recommend that you look at the voltages on your model at the time the problem occurs and look for discontinuous behavior.

-Ken

Title: Re: Writing Capacitance model with charge conservation principle
Post by Geoffrey_Coram on Jul 8^th, 2011, 5:55am

Let's look at only Q_GS and its derivative, assuming v_GS = V(g,s)

Code:

if (v_GS >= vth) begin
Q_GS = C_sov*v_GS;
// cgs = C_sov;
end else if ((v_DS) > v_GS-vth) begin
Q_GS = (C_ch/2)*(v_GS-vth) + C_sov*vth;
// cgs = C_ch/2
end else begin
Q_GS = (1/2)*C_ch*(v_GS-vth) + C_sov*vth;
// cgs = C_ch/2
end

So, your charge may be continuous, but its derivative is not, and since Spice-like simulators use Newton's method to find solutions, it is important to have continuity of derivatives.

Title: Re: Writing Capacitance model with charge conservation principle
Post by Geoffrey_Coram on Jul 8^th, 2011, 6:06am

kumar.g wrote on Jul 6^th, 2011, 12:49pm:

I have some more eqns for the static behaviour. Those r basic MOSFET eqns from any book. I dont think the problem comes from those eqns.

You might want to try turning off the capacitance equations -- maybe add just a linear capacitor to the gate (or set C_ch=0 and let C_sov and C_dov be non-zero).