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Simulators >> AMS Simulators >> How to do Verilog/VerilogA co-simulation , using cadence ams ? urgent
https://designers-guide.org/forum/YaBB.pl?num=1309486760

Message started by dongzz201 on Jun 30^th, 2011, 7:19pm

Title: How to do Verilog/VerilogA co-simulation , using cadence ams ? urgent
Post by dongzz201 on Jun 30^th, 2011, 7:19pm

How to do the ams simulation , using verilog + verilogA ?

Now My top cell is verilog file, in which the analog sub-module is instantiated.

1. The analog sub-module is SPICE netlist.
I can run the ams simulation.
The amsd block is :
include "./source/ana_cell.spi" ( SPICE netlist file )
amsd {
ie vsup=1.8
portmap subckt=ana_cell
config cell=ana_cell use=spice
}

2. The analog sub-module is verilogA file .

My amsd block is :
ahdl_include "./source/ana_cell.va" ( VerilogA file )
amsd {
ie vsup=1.8
}

Then the simulator always give me an error :
" Could not determine discipline for xx.xx.xx "

how to create the right amsd block ?

Urgent!

Title: Re: How to do Verilog/VerilogA co-simulation , using cadence ams ? urgent
Post by ywguo on Jul 1^st, 2011, 6:21am

Hi donzz201,

I don't think that you define connect rules for your simulation model. I came across a similar problem in 2008. Please click the following link for details.
http://www.designers-guide.org/Forum/YaBB.pl?num=1230197093/2#2

Best Regards
Yawei

Title: Re: How to do Verilog/VerilogA co-simulation , using cadence ams ? urgent
Post by dongzz201 on Jul 3^rd, 2011, 6:20pm

Thanks for your reply!
i am also confused after reading your comments.
I think , since using SPICE netlist, i can run ams correctly, the connect-rules should be already found.
I do not understand that the ams do not run after using the verilog-A files to replace the original SPICE netlist.

So the amsd block may not been correctly defined.
please give more ideas.