The Designer's Guide Community Forum

The Designer's Guide Community Forum
https://designers-guide.org/forum/YaBB.pl
Design >> Analog Design >> Design fully differential folded-cascoded OTA
https://designers-guide.org/forum/YaBB.pl?num=1309960586

Message started by juneja on Jul 6^th, 2011, 6:56am

Title: Design fully differential folded-cascoded OTA
Post by juneja on Jul 6^th, 2011, 6:56am

Hi all!

I am afraid i'm seriously new to analog design but have got my first assignment to designing of a fully differential folded-cascoded OTA. Can someone kindly guide me, or give some link to a step by step design tutorial? I'm implementing a configuration with a pmos differential input stage.

Thanks for help!

Title: Re: Design fully differential folded-cascoded OTA
Post by raja.cedt on Jul 6^th, 2011, 8:48am

hello,
it is difficult explain how select each and every device device size, though you are fresher for circuit design better start using Gm/Id methodology. Try to characterize technology and get all the plot required for your specs.

Thanks.

Title: Re: Design fully differential folded-cascoded OTA
Post by juneja on Jul 7^th, 2011, 2:01am

Thanks.

I am trying to do simulations on Cadence using UMC 180 nm technology. kp=180, kn=70uA/V.

My circuit is a pmos diff input stage. It has a Output CMFB circuit also, and I don't know at all how to go ahead with it.

Can you please help?

Title: Re: Design fully differential folded-cascoded OTA
Post by harpoon on Jul 26^th, 2011, 8:35am

pls read baker and li book ... cmosedu.com

his approach is to use the same W/L for most if not all PMOS and likewise for NMOS ... which is a good start.

also, if you can get some material from w. sansen, that would be another start.

Things to consider :-
- gm/Id ~ 10 for your input devices, lower for speed and higher for gain.
- unity gain bandwidth - this will determine the gm of your input stage.
- compensation scheme to stabilize differential path. Try not to use miller compensation, there are better ways. Again refer to cmosedu.com
- cmfb should also be considered very carefully ... often under-estimated ...
- noise
- slew rate

Title: Re: Design fully differential folded-cascoded OTA
Post by RobG on Jul 27^th, 2011, 4:52pm

I don't know why this is made to be such a big deal by the various authors. gm/Id is so "non physical." On the other hand 2*Id/gm is about Vgs-Vt, which is just the overdrive of the transistor. It is how much headroom the MOS needs. It is what you need to consider to fit the design between the rails. It is physical. gm/Id is just a number that needs further adjustment to make it useful. That is to say, to convert it to Vgs-Vt. So why not start with Vgs-Vt?

For design, I use the cadence parameter vdsat as a proxy for Vgs-Vt. The first pass at a design is pretty simple:
1) Set your diff pair and cascode vdsat to 150mV to maximize its gm (less vdsat than that gives diminishing returns as it enters weak inversion)
2) Set the current mirror vdsat as large as headroom will allow (say 300 mV). This will minimize its gm.
3) If you have a second stage, maximize its gm by setting vdsat=150mV.
4) Cascode devices usually have the same width as the device it is cascoding, but a shorter length.

Note that gm ~2I/(Vgs-Vt). (Or I/nUt if in weak inversion). Use that to figure out what your tail current needs to be to get the bandwidth or noise that you need. Similarly the output stage current is determined by the gm required to push the 2nd pole out enough to give phase margin.