The Designer's Guide Community Forum
https://designers-guide.org/forum/YaBB.pl Modeling >> Semiconductor Devices >> IBM45nm (SOI ) technology Gate resistance problem https://designers-guide.org/forum/YaBB.pl?num=1311007671 Message started by nadroit on Jul 18th, 2011, 9:47am |
Title: IBM45nm (SOI ) technology Gate resistance problem Post by nadroit on Jul 18th, 2011, 9:47am I am using IBM45nm (SOI) technology provided by MOSIS for designing RF circuits. I used cadence 6.1 to carry out some simulations. When I do typical DC simulation and print the oprating points I do not see the value for gate resistance . Why is this happning? is there no gate resistance in SOI technology? (I checked the BSIMSOI manual and they do model gate resistance and ther RF parameters) I bit confused please help. Thanks |
Title: Re: IBM45nm (SOI ) technology Gate resistance problem Post by Geoffrey_Coram on Jul 20th, 2011, 6:36am Did you check the documentation for BSIMSOI in your simulator and verify that RG or RGEFF or whatever is in the list of operating point values? |
The Designer's Guide Community Forum » Powered by YaBB 2.2.2! YaBB © 2000-2008. All Rights Reserved. |