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Design >> Mixed-Signal Design >> a ridiculous 'overshoot'
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Message started by chaojixin on Jul 26^th, 2011, 6:43pm

Title: a ridiculous 'overshoot'
Post by chaojixin on Jul 26^th, 2011, 6:43pm

I encounter a ridiculous 'overshoot' in a PGA design as shown in (B) which is is quite different from the normal overshoot as shown in (C). the phase margin is enough (80 degree), and the opamp is a cascode + gain-boost structure. but when I reduce the W/L of input MOS pair and keep bias current unchanged, the response of Vo becomes normal as shown in (D).
what does this ridiculous 'overshoot' come from? is it something to do with the parameter setting of input MOS pair?

thanks!

Title: Re: a ridiculous 'overshoot'
Post by Alexandar on Jul 27^th, 2011, 2:37am

First of all, let me ask u whether your transient repsonses are small signal, or large signal. For large signals, you might get some slewing effect in the way. If you simulated a small signal, I think this kind of overshoot should be predictable by AC analysis.

Title: Re: a ridiculous 'overshoot'
Post by RobG on Jul 27^th, 2011, 4:29pm

That looks like a zero in the transfer function not being cancelled exactly by a pole (i.e. a pole/zero doublet).

Title: Re: a ridiculous 'overshoot'
Post by chaojixin on Jul 27^th, 2011, 10:51pm

I forgot something: it is large signal response. the ridiculous 'overshoot' is only several mV and its location is very closed to steady state value. but it did slow down the setting up

chaojixin wrote on Jul 26^th, 2011, 6:43pm:

Title: Re: a ridiculous 'overshoot'
Post by wave on Jul 28^th, 2011, 1:18pm

What "large signal" amplitude are you putting in?
It could be you are slewing most of the way and small signal is not relevant.

Title: Re: a ridiculous 'overshoot'
Post by loose-electron on Aug 4^th, 2011, 7:55am

It can also be a transient from input to output capacitively coupling thru the transistors.

If you are trying a "step response" you will see the step couple through system.