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Simulators >> Circuit Simulators >> SPICE and the leakage current
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Message started by UVSoft on Aug 9^th, 2011, 8:23am

Title: SPICE and the leakage current
Post by UVSoft on Aug 9^th, 2011, 8:23am

Hello,

I am sorry if I repeat the same question over and over again, but I have honestly tried to find an answer here, there is something, but still it is not that clear for me. I am new to this area, please excuse my misunderstanding.

So, I would like to measure the leakage current using SPICE (to be precise, I am using NGSPICE) for a CMOS NAND gate, or at least for a separate NMOS or PMOS. In order to do this, I took the BSIM4 model with all the parameters and made a simple circuit. Here is its listing (one NMOS):

Code:

Measure the leakage current of a CMOS NAND gate

.param length = 65n
.param width = 10u
.param vdd = 1
.param vg = 0

.options noacct

m1 d g s b n1 l={length} w={width}

vds d s {vdd}
vgs g s {vg}
vbs b s 0
vss s 0 0

.control
op
print vbs#branch
print vds#branch
print vgs#branch
print vss#branch
print @m1[id]
print @m1[ibd]
print @m1[ibs]
print @m1[isub]
print @m1[igs]
print @m1[igd]
print @m1[igb]
print @m1[igcs]
print @m1[igcd]
.endc

.include modelcard.nmos
.include modelcard.pmos

.end

Since NMOS is off then the gate voltage is low, Vg is set to zero (we are measuring the leakage current what the device is turned off). So, it gives me something like:

Code:

vbs#branch = 7.340167e-11
vds#branch = -1.02761e-07
vgs#branch = 9.773162e-08
vss#branch = -5.85230e-23
@m1[id] = 4.955657e-09
@m1[ibd] = -7.34015e-11
@m1[ibs] = 0.000000e+00
@m1[isub] = 1.593217e-16
@m1[igs] = 2.510354e-18
@m1[igd] = -9.77316e-08
@m1[igb] = 2.497680e-23
@m1[igcs] = 3.422269e-20
@m1[igcd] = 3.384294e-20

Can anybody please explain me what is going on here? Why the first commands are so different from the direct reading of the device's parameters? What is the real subthreshold leakage current and where is the total gate leakage current?

Yet another question, how to measure the same, but for a NAND gate. The problem is that I cannot understand what will be a complete off state here, because we have two pair of MOSs of different types, so if we switch off NMOSs, PMOSs will be on, and vise versa.

And the last question, is it possible to plot the device's parameters (@m1[...]) with a dc-sweep? When I do like "plot @m1[isub]" after "dc ...", it plots a straight line, since @m1[...] is just one value, I guess at the last point of the dc sweep.

Thank you.

Best wishes,
Ivan

Title: Re: SPICE and the leakage current
Post by boe on Aug 9^th, 2011, 8:40am

UVSoft,

The currents through the terminals of the transistor consist of several components. If you add all operating point components that connect, say, to the drain, - with the appropriate sign, of course - you get the drain current: 4.955657e-09 + 7.34015e-11 + 9.77316e-08 = 1.02761e-07.

B O E

Quote:

vds#branch = -1.02761e-07

@m1[id] = 4.955657e-09
@m1[ibd] = -7.34015e-11
@m1[igd] = -9.77316e-08

Title: Re: SPICE and the leakage current
Post by UVSoft on Aug 9^th, 2011, 1:15pm

boe wrote on Aug 9^th, 2011, 8:40am:

vds#branch = -1.02761e-07

@m1[id] = 4.955657e-09
@m1[ibd] = -7.34015e-11
@m1[igd] = -9.77316e-08

Thank you, Boe, now this part is clear. It is nice to have such quick responses, I do appreciate it. I would like to ask you some more questions if you do not mind.

So, I know that the main parts of the leakage current are the subthreshold leakage and the gate leakage. Am I right that the first one is this vds#branch, everything that goes through the drain? But what is this @m1[isub] then, it quite differs.

Now about the gate leakage. This current "results from tunneling between the gate terminal and the other three terminal (source, drain, and body)". So, @m1[igd] should be a part of the gate leakage, no? Or it just consists of @m1[igb] (to the body), @m1[igcs] (to the source through the channel), and @m1[igcd] (to the drain through the channel)? Correct me if I wrong, but I suppose @m1[igd] is due to the overlapping part between the drain and the insulator, so not through the channel.

And the last thing, why the current from the source is so small (vss#branch), I thought what it was where everything ended up.

Thank you.

Title: Re: SPICE and the leakage current
Post by UVSoft on Aug 9^th, 2011, 3:03pm

According to the manual of the BSIM4 model, the gate leakage has three components: Igb (tunneling to substrate), Igc = Igcs + Igcd (tunneling to channel), and Igs + Igd (diffusion regions). But Igd in our case is negative, how am I supposed to sum them up? And the subthreshold leakage should be only Id, but what about Ibd. By the way, Isub here is the substrate current, not subthreshold or something.

Title: Re: SPICE and the leakage current
Post by boe on Aug 10^th, 2011, 2:04am

UVSoft,

Id = Ids, so: opposite sign of Igd and Ibd.
And regarding Ig, all components but Igd are negligible anyway.

Note the default direction: current into ports is positive.

B O E

Title: Re: SPICE and the leakage current
Post by Geoffrey_Coram on Aug 16^th, 2011, 5:54am

UVSoft wrote on Aug 9^th, 2011, 1:15pm:

And the last thing, why the current from the source is so small (vss#branch), I thought what it was where everything ended up.

You have all your voltage sources (vds, vgs, vbs) tied to "s", and the only connection to ground (node 0) is vss, so the current reported for vss is actually showing you numerical error in KCL. Sketch out a schematic and it will be obvious.

Title: Re: SPICE and the leakage current
Post by boe on Aug 17^th, 2011, 3:02am

UVSoft,
UVSoft wrote on Aug 9^th, 2011, 8:23am:

... Yet another question, how to measure the same, but for a NAND gate. The problem is that I cannot understand what will be a complete off state here, because we have two pair of MOSs of different types, so if we switch off NMOSs, PMOSs will be on, and vise versa. ...

For any standard static CMOS gate, the on transistors pull the output to VDD or VSS, so (for a capacitive load) there will be no current through them (except the leakage current of the transistors that are off).

UVSoft wrote on Aug 9^th, 2011, 1:15pm:

... I know that the main parts of the leakage current are the subthreshold leakage and the gate leakage. Am I right that the first one is this vds#branch, everything that goes through the drain? But what is this @m1[isub] then, it quite differs. ...

vds#branch is the current into the Drain, consisting of channel (leakage) current (Drain-Source), the Drain-Bulk diode leakage, the Gate-Drain overlap isolation leakage and the Gate-Channel leakage.

Concerning Gate leakage, all components but Igd are negligible anyway (more that 10 orders of magnitude smaller!), way beyond what can be measured (Igs is ca. 15 electrons per second!).

Hope this helps,
B O E