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Simulators >> RF Simulators >> PLL time domain simulation
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Message started by .matteo on Aug 12^th, 2011, 1:51am

Title: PLL time domain simulation
Post by .matteo on Aug 12^th, 2011, 1:51am

Hi everybody,
I designed a PLL and I would like to double check everything works by doing a time domain simulation of the whole thing. I have 2 questions:

1) Do you have any suggestion about how to speed up the simulation? Any of your previous experience comment is welcome.
2.a) I realized a verilog model for my VCO. Since the VCO is followed by a prescaler and a divide-by-n block, I set the output frequency of the VCO as: f_out = f_reference + K*(v_in - 600e-3), where K is the Kvco of my VCO divided by the prescaler division ratio and then by the divide-by-N division ratio. Do you think this approach is correct? By looking at the equation of the PLL I would say yes but I would like to hear the opinion of somebody else.
2.b) I used this verily model to simulate the closed-loop PLL. Is this correct?

Thank you very much,
Matteo

Title: Re: PLL time domain simulation
Post by .matteo on Aug 22^nd, 2011, 1:59am

any idea?

Title: Re: PLL time domain simulation
Post by raja.cedt on Aug 22^nd, 2011, 5:26am

hello,
for sanity check you can run whole PLL in time domain if you want to see how locking is happening. How big your PLL means do you have any auxillary circuitary is there? But according your question equation is looks correct for me. In general people do this verilog a modeling or some kind behaviour modling in most of the noise simulation because it's difficult to run PSS on big circuit.

Just an advice, if you go to cadance verilog models..there is an well developed VCO code.

Thanks.

Title: Re: PLL time domain simulation
Post by sheldon on Oct 8^th, 2011, 7:09pm

Matteo,

Spectre RF supports a technology called the Noise-Aware PLL flow.
It is an automated tool for PLL behavioral modeling. The key is the
VCO model. It will allow you to replace VCO with a behavioral model
and still make a good estimate of PLL characteristics, for example,
phase noise. While you can simulate at the behavioral level, my usual
configuration is PFD/CP/loop filter at transistor level and VCO/divider
at behavioral level. This gives a good speed-up and captures most of
the nasty non-idealities in the loop: charge pump mismatch, etc. Most
of my test data has a 2x VCO so I include the divide by 2 in the
VCO characterization. One other comment, you will need to set the
VCO number of points per period to a reasonable value. I like 50
but you can get away with less. If you have access and want more
information there have been several presentations at CDNLive over
the years on the technology.

Best Regards,

Sheldon