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https://designers-guide.org/forum/YaBB.pl Design >> Analog Design >> Two ways to test the linearity of a Switched Capacitor Integrator? Which is bett https://designers-guide.org/forum/YaBB.pl?num=1313210248 Message started by sharezhao on Aug 12th, 2011, 9:37pm |
Title: Two ways to test the linearity of a Switched Capacitor Integrator? Which is bett Post by sharezhao on Aug 12th, 2011, 9:37pm Dear all: The switched capacitor integrator is as following. how to test the linearity of the integrator? I am consid[img][/img]ering to do it in following way. 1) Input is a pure sin wave, the do pss+pac, then calculate the iip3 2) input is a pure sin wave, the output is a stair-case sin wave, then sample the output and do DFT then watch the HD3. Which way is better? Anyone watch this post must leave you idea. LoL!! Thank you for your attention!!! |
Title: Re: Two ways to test the linearity of a Switched Capacitor Integrator? Which is bett Post by harpoon on Aug 16th, 2011, 1:35am I am about to embark on a similar design ... have you tried both methods ? Does the result differ between the methods ? For switched cap designs, I am very wary of PSS sims and will trust the transient + DFT/FFT results more. My guess is that the more accurate way to simulate this is to use transient noise sims, but have not looked into that yet. |
Title: Re: Two ways to test the linearity of a Switched Capacitor Integrator? Which is bett Post by vivkr on Aug 18th, 2011, 7:01am sharezhao wrote on Aug 12th, 2011, 9:37pm:
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