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Design >> Analog Design >> low Vt sub-threshold design ?
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Message started by The Falcon on Aug 23^rd, 2011, 8:23am

Title: low Vt sub-threshold design ?
Post by The Falcon on Aug 23^rd, 2011, 8:23am

Hi

is it reliable to design analog circuits with Low Vt MOS for new tech like 65nm or 90nm
i mean also " are the models reliable ?"
any paper or links are highly welcomed

Thanks

Title: Re: low Vt sub-threshold design ?
Post by raja.cedt on Aug 23^rd, 2011, 9:33am

hello,
you should ask this question to fab. For low Vt design refer to anatha chandrakasan reserch group.

Title: Re: low Vt sub-threshold design ?
Post by Larry_80 on Aug 23^rd, 2011, 3:45pm

I believe you can, if your primary concern is low power instead of speed. But i will encourage you to do more research on this since from your question, you are relatively new in this area!

Title: Re: low Vt sub-threshold design ?
Post by Larry_80 on Aug 23^rd, 2011, 7:36pm

If the model file has your transistors modeled as subckts, then u can absolutely trust the models, if not then you cannot!

Title: Re: low Vt sub-threshold design ?
Post by harpoon on Aug 24^th, 2011, 1:09am

I can only say that it depends on foundries.

Generally, a lot of the foundry effort goes into getting the nominal devices to work ... and for an analogue kit, the effort is for getting the modelling right for "normal" operation of nominal devices.

A good indicator is to check how many "msmt vs sim" plots you get for those devices compared to a nominal device.

Also process control is tighter for the nominal Vt devices as that is the main device in any foundry offering (i think ?).

You will probably see a hit in yield if designing using low-vt + subthreshold for "critical" cells.

having said all that, do go for it ! Design is all about pushing the boundaries ... as long as you understand the risk you are taking !

good luck !