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Design >> Mixed-Signal Design >> fractal sequencing to cancel offset in delta sigma ADC
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Message started by singh on Sep 2^nd, 2011, 7:40am

Title: fractal sequencing to cancel offset in delta sigma ADC
Post by singh on Sep 2^nd, 2011, 7:40am

can some explain me how we can use fractal sequencing to nullify offset in second order delta sigma ADC?

thanks

Title: Re: fractal sequencing to cancel offset in delta sigma ADC
Post by vivkr on Sep 5^th, 2011, 5:45am

singh wrote on Sep 2^nd, 2011, 7:40am:

can some explain me how we can use fractal sequencing to nullify offset in second order delta sigma ADC?

thanks

why not look it up in the original reference which explains it fairly well if I recall correctly: JSSC, July '06, Quiquempox et. al. A Google search leads you straight to the paper:

www.mit.bme.hu/~markus/pubs/jssc2006.pdf

Vivek

Title: Re: fractal sequencing to cancel offset in delta sigma ADC
Post by singh on Sep 6^th, 2011, 7:23am

oh thanks...

how can we apply fractal sequencing method to mullify offset in the input signal...any idea?

it will be great if some one can provide me a brief matlab implementation for that as i m new to matlab.

Title: Re: fractal sequencing to cancel offset in delta sigma ADC
Post by singh on Sep 7^th, 2011, 7:22am

the link which u have given above is describing fractal sequencing.But how it is applied in the circuit (fig 5) of the paper.

please explain me briefly..it will be very helpful.

Title: Re: fractal sequencing to cancel offset in delta sigma ADC
Post by vivkr on Sep 8^th, 2011, 11:43pm

not quite sure what you want to know. Fig. 5 not only shows the exact manner in which you need to add the chopping switches, but also the fractal timing sequence to control those. I doubt if it is possible to explain it better in words.

Maybe you should try reading the paper a couple more times to get a grasp of it, or if you are not familiar with such circuits, then seek out a colleague of yours who is.

Vivek

Title: Re: fractal sequencing to cancel offset in delta sigma ADC
Post by singh on Sep 9^th, 2011, 5:35am

Thanks..

I have offset in my input signal due to previous stage and this input+offset is fed to integrator of sigma delta .Thus i need to compensate both the offsets.

So the same circuitary is applicable to nullify the total offset (due to input and due to integrator)?

I am a third year student in bachelors and i think i have taken a tough project. :-/

Title: Re: fractal sequencing to cancel offset in delta sigma ADC
Post by vivkr on Sep 12^th, 2011, 1:53am

if you have an offset in your input signal, then this is now part of the signal itself. you cannot get rid of it using chopper stabilization or fractal sequencing. The whole idea behind all these methods is that you don't disturb the input signal and retain all of it including any DC component, but simply modulate the offset of the circuitry operating on the signal.

If you need to get rid of offset contained within the input, then you would need to so something else. The easiest thing that comes to my mind is to apply chopper stabilization or fractal sequencing to whatever circuit is providing your input signal in this case. I doubt if you can simply get rid of the offset by directly filtering it as you would then lose any low-frequency information contained in the signal, which in your case is likely to be relevant.

On a side note, maybe you have taken up a tough task, but you will probably gain more if you do pull it off. Ever heard of "no pain, no gain"?

Regards
Vivek

Title: Re: fractal sequencing to cancel offset in delta sigma ADC
Post by singh on Sep 12^th, 2011, 4:35am

Thanks vivek for your valuable suggestions

i referred on document

http://www.patentgenius.com/patent/6909388.html

this is the reference paper for the one u provided me for fractal sequencing.here they say that the approach is used to separate offset from the input signal (page 7)

before this sigma delta ADC, I am using an integrator which is setting an offset to my input signal to SD ADC.This offset is mainly due to feedback capacitor KT/C noise.

I was also thinking to give a shot applying fractal sequencing to this integrator block.

the offset due to KT/C is around 20 mV. Is it not possible to use the first stage of DS ADC integrator to nullify the offset. But point is like how the circuit will distinguish input offset value from Input signal as both (input+inp offset) will be stored in capacitor cin (fig 5 of paper ) and will be supplied as combined input to integrator phase of ADC?

regards
manjeet

Title: Re: fractal sequencing to cancel offset in delta sigma ADC
Post by vivkr on Sep 13^th, 2011, 5:48am

singh wrote on Sep 12^th, 2011, 4:35am:

Manjeet,

There are several points to be made here:

1. As you correctly noticed, it is not possible to separate signal from offset once this "offset" is embedded into the signal, atleast not without removing the low-frequency part of the signal itself, which you don't want to do I suppose. But what you are talking about is anyway not offset. See point 2.

2. kT/C noise is not an offset. It is caused by sampling of wideband thermal noise. Also, you need to use metrics such as standard deviation to specify this noise. On a side note, I do hope that you do not have a standard deviation of 20 mV (given as sqrt(kT/C)), as that would be highly unlikely for most realistic values of C.

It seems to me that you are not yet familiar with concepts related to noise at the moment, which is understandable if you still an undergrad. But perhaps you want to talk to your professor and get his advice on how best to approach the problem at hand.

Vivek