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Design >> Analog Design >> SB-PLL - Jitter Vs. V1
https://designers-guide.org/forum/YaBB.pl?num=1315370375

Message started by HereWe on Sep 6^th, 2011, 9:39pm

Title: SB-PLL - Jitter Vs. V1
Post by HereWe on Sep 6^th, 2011, 9:39pm

Hi
I measured timing jitter of SB-PLL, and saw that once increasing the PLL CLK output (by programming the feedback counter) the jitter decrease.
I guess it is related to the RO device Vth, (V1 vs. Vth)

any comments or other theory on this will be pleased, thanks!

Title: Re: SB-PLL - Jitter Vs. V1
Post by raja.cedt on Sep 7^th, 2011, 12:59am

hello,
what do you mean by SB-pll. Any how if you are asking for normal pll, by increasing Feedback divider all refclk jitter, pfd-cp phase noise will get amplified. So area under the curve will increase, hence more timing jitter. But you have to see how your VCO noise is changing. So for this type questions you should really plot all phase noise with appropriate noise transfer functions and get the area under the curve.

Thanks.

Title: Re: SB-PLL - Jitter Vs. V1
Post by loose-electron on Sep 12^th, 2011, 10:05am

please make a clear question. Drawings and equations to describe are a good thing to have.