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Message started by LaTeX on Sep 8th, 2011, 11:46pm

Title: How to choose transistor sizes in CMOS PA
Post by LaTeX on Sep 8th, 2011, 11:46pm

HI,
   I'm design a 65nm CMOS PA for WiMax with on-chip transformer as the output impedance transformation network. The maximum output power is larger than 30dBm. I'm confusing that how to choose the transistor sizes. As we know, if the output power is very large, transistor sizes must be large too. But how can I know what the accurate sizes are with an fixed maximum output power?

Thank you!  

Title: Re: How to choose transistor sizes in CMOS PA
Post by prakash@191 on Oct 19th, 2011, 12:17pm

The length of the transistor should be not changed as far as i know. Because the technology has to to maintained constant.
For the less power dissipation you should have more width for a given transistor.
Let me know what you mean by accurate sizes.

Title: Re: How to choose transistor sizes in CMOS PA
Post by watson822 on Oct 26th, 2011, 3:56am

I have this question before. In my opinion, under fixed Vcc and required output power, you can get bias current Ic from load-line principle. Then, choose transistor size based on the current density of metal trace.

Title: Re: How to choose transistor sizes in CMOS PA
Post by LaTeX on Oct 26th, 2011, 4:56am


prakash@191 wrote on Oct 19th, 2011, 12:17pm:
The length of the transistor should be not changed as far as i know. Because the technology has to to maintained constant.
For the less power dissipation you should have more width for a given transistor.
Let me know what you mean by accurate sizes.


I mean when supply voltage and maximum saturated power is given, how can I choose the transistor width? thx

Title: Re: How to choose transistor sizes in CMOS PA
Post by LaTeX on Oct 26th, 2011, 4:59am


watson822 wrote on Oct 26th, 2011, 3:56am:
I have this question before. In my opinion, under fixed Vcc and required output power, you can get bias current Ic from load-line principle. Then, choose transistor size based on the current density of metal trace.

would you give some suggestions for the load-line simulation?
how to set the simulation load R? R equals Rload? or the optimum Ropt?

Thank you!

Title: Re: How to choose transistor sizes in CMOS PA
Post by loose-electron on Oct 26th, 2011, 11:49am

A load line?
That is not a simulation. Please look the subject
up in a basic transisotr level design textbook.

This is going to be a good way to get a basic operating point for a first pass at the design.

To be more helpful, you need to be more
specific about what you need.

Title: Re: How to choose transistor sizes in CMOS PA
Post by weber8722 on Nov 17th, 2011, 8:23am

The load line concept is good for PA's! I would look at the transistor saturation voltage. If it should be low for good efficiency (like 150mV), than maybe the transistor Cgs becomes large and speed, gain low. So a compromise it needed - also for best reliability. At the end not all can be really simulated... :-?

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