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Simulators >> AMS Simulators >> E2L convert one analog rising edge into two edges in digital domain
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Message started by ywguo on Sep 16^th, 2011, 7:14am

Title: E2L convert one analog rising edge into two edges in digital domain
Post by ywguo on Sep 16^th, 2011, 7:14am

Hi Guys,

I simulate a verilog model for divider-by-2. The input signal is vpulse in analogLib. An E2L connect module is inserted automatically. I found that the output is weird. Sometimes there are very very narrow pulses at the output, sometimes there are not any pulse. The pulse width is equal to delta T defined by timescale, for example, 100ps.

The verilog code for divider-by-2 is shown below. The input clock signal mclk_150k is monitored with display task.

Code:

`include "constants.vams"
`include "disciplines.vams"

module div2 ( clk_cic, pdb, mclk_150k );

output clk_cic;
input pdb;
input mclk_150k;

reg clk_cic;

always @(posedge mclk_150k or negedge pdb) begin
$display($time, "ns mclk_150k rises");
if (~pdb)
clk_cic <= 1'b0;
else
clk_cic <= ~clk_cic;
end

endmodule

The simulation log file reveals that there are two rising edges in digital domain at the analog rising edge.

Code:

1ns mclk_150k rises
1ns mclk_150k rises
tran: time = 2.557 us (2.56 %), step = 443.6 ns (444 m%)
6001ns mclk_150k rises
6001ns mclk_150k rises
tran: time = 8.332 us (8.33 %), step = 1 us (1 %)
12001ns mclk_150k rises
12001ns mclk_150k rises
tran: time = 12.67 us (12.7 %), step = 332.8 ns (333 m%)
tran: time = 18 us (18 %), step = 667.4 ns (667 m%)
18001ns mclk_150k rises
18001ns mclk_150k rises

The tools version are ic 5.1.41 isr20100624, mmsim 07.20.194, and ius 09.20.s008.

What's wrong with my model? Any comments are appreciated.

Yawei

Title: Re: E2L convert one analog rising edge into two edges in digital domain
Post by boe on Sep 16^th, 2011, 8:29am

Ywguo,

First of all, mmsim 07.20.194 is fairly old. Did you try a recent version?
I checked the code of the standard E2L module and it seemed OK, so perhaps a simulator bug?
However, a few additional ideas: What parameters do you use for in your connect rules? Which rules do you use? Is supply present?

B O E

Title: Re: E2L convert one analog rising edge into two edges in digital domain
Post by ywguo on Sep 18^th, 2011, 6:39am

Hi B O E,

I don't think that has nothing to do with mmsim. Anyway, I tried mmsim 10.11.056 in the morning.

It seems that is related to my E2L module. It is not the standard E2L module in IUS. But it is very similar. I will update asap.

Thanks
Yawei

Title: Re: E2L convert one analog rising edge into two edges in digital domain
Post by ywguo on Sep 18^th, 2011, 9:45pm

Hi,

A vpulse signal was fed to clock signal of div2, the rise time and fall time are 1ns. The output of E2L_2_inhconn module became x and 1 almost simultaneously at the rise edge of analog voltage pulse. Unfortunately, ncsim regards that 0 -> X as posedge. So the divider by 2 goes up and down. No pulse is visible or there are very very narrow pulse. The width is determined by delta T defined by timescale.

I looked into this E2L_2_inhconn.vams file and E2L_2_inhconn.vams file in IUS installation directory. The have minor differences, but I think they shall have the same function. However, if I replace myconnectLib with connectLib in IUS installation directory, everything works fine. There are not any X.

The delay to find out X are 0.8ns in both E2L_2_inhconn module. So I think 1ns rise time and fall time is sharp enough to avoid X. But it fails for myConnectlib and works for connectLib in IUS install directory.

The following is part of my E2L_2_inhConn module.

Code:

// INSTANCE PARAMETERS:
parameter real vsup_min=0.5 from (0:inf); // min supply for normal operation
parameter real tr=0.2n from (0:1m); // risetime (for defaults)
parameter real txdel=4*tr from (0:1m); // time midrange til output X
parameter real ttol_c=tr/4 from (0:1m); // time tolerance of crossing
parameter real tf=tr from (0:inf); // falltime of analog output
parameter real ttol_t=(tr+tf)/20 from (0:inf); // time tol of transition
parameter real tdelay=0 from [0:inf); // delay time of analog output
// scaled input/output levels/thresholds (0 maps to Vref, 1 maps to Vsup):
parameter real vthi=1/1.5 from (0:1); // frac. for high tresh (def=2/3)
parameter real vtlo=vthi/2 from (0:vthi); // frac. for low tresh (def=1/3)
parameter real vtol=1.0/12 from (0:(vthi-vtlo)/2]; // frac. for vtol
parameter real vtlox=vtlo+vtol from (vtlo:vthi); // lo to X state threshold
parameter real vthix=vthi-vtol from [vtlox:vthi); // hi to X state threshold
// LOCAL VARIABLES:
reg Dreg; // output register
reg Xin; // Tx control registers
real Vds; // supply voltage
real Vas; // input voltage
real Vdsflag; // flag if Vds exceeds vsup_min
real Kin; // input relative to supply range
real txdig; // tx in timescale units

//============================================================================
initial begin
txdig=txdel/1n; // digital delay midlevel to X (ASSUMES TIMESCALE)
Dreg=1'b0; // initial level
Xin=0; // initially not in X delay region.
end

// Relative input level (maps input to range of 0=vref, 1=vsup):
// analog begin
// Vdsflag = V(\vdd! ,\vss! ) > vsup_min;
// Kin = V(Ain,\vss! )/max(V(\vdd! ,\vss! ),1m) * transition(Vdsflag,tdelay,tr,tr,ttol_t);
// end

// Convert analog signal to high/low and X/notX:
always @(above(Kin-vthi,ttol_c,vtol))
begin Dreg=1; Xin=0; $display($time, " ns, Dreg=1"); end // analog XtoH
always @(above(vtlo-Kin,ttol_c,vtol))
begin Dreg=0; Xin=0; $display($time, " ns, Dreg=0"); end // analog XtoL
always @(above(vthix-Kin,ttol_c,vtol)) begin
$display($time, " ns, Dreg==1'b1, Xin=1");
if (Dreg==1'b1) Xin=1; // analog HtoX
end
always @(above(Kin-vtlox,ttol_c,vtol)) begin
$display($time, " ns, Dreg==1'b0, Xin=1");
if (Dreg==1'b0) Xin=1; // analog LtoX
end
// Wait for txdel before driving output to X:
always @(posedge(Xin)) begin // input changed to X
#(txdig) // wait for X time delay
if (Xin==1) begin
Dreg=1'bx; // goto X if still between
$display($time, " ns, Dreg=%b", Dreg);
end
end
assign Dout=Dreg; // assign register to output
always @(posedge Dreg) begin
$display($time, " ns, Dreg rises");
end
always @(negedge Dreg) begin
$display($time, " ns, Dreg falls");
end
// Relative input level (maps input to range of 0=vref, 1=vsup):
analog begin
Vds = V(\vdd! ,\vss! );
Vas = V(Ain,\vss! );
Vdsflag = Vds > vsup_min;
Kin = Vas/max(Vds, 1m) * transition(Vdsflag,tdelay,tr,tf,ttol_t);
end

Title: Re: E2L convert one analog rising edge into two edges in digital domain
Post by ywguo on Sep 18^th, 2011, 9:57pm

The following is part of the simulation log and the waveform, where mclk_150k is clock input, and clk_cic is the output of div-by-2.

Code:

Warning from spectre in `cds_globals', during circuit read-in.
`cds_globals': Parameter `power' redefines parameter of same name defined
at higher level.
`cds_globals': Parameter `Ts' redefines parameter of same name defined at
higher level.

Circuit inventory:
nodes 4
csmc05mm01_connectLib+E2L_2_inhconn+module+0x10000001 behavioral 2
vsource 4

************************************************
Transient Analysis `tran': time = (0 s -> 15 us)
************************************************
0 ns, Dreg==1'b1, Xin=1
0 ns, Dreg=0
0 ns, Dreg==1'b1, Xin=1
0 ns, Dreg=0
0ns mclk_150k rises, mclk_150k=0
0ns mclk_150k rises, mclk_150k=0
Important parameter values:
start = 0 s
outputstart = 0 s
stop = 15 us
step = 15 ns
maxstep = 150 ns
ic = all
skipdc = no
reltol = 100e-06
abstol(I) = 1 pA
abstol(V) = 1 uV
temp = 27 C
tnom = 27 C
tempeffects = all
errpreset = conservative
method = gear2only
lteratio = 10
relref = alllocal
cmin = 0 F
gmin = 1 pS

0 ns, Dreg==1'b0, Xin=1
1 ns, Dreg=x
1 ns, Dreg rises
1ns mclk_150k rises, mclk_150k=x
1 ns, Dreg=1
1 ns, Dreg rises
1ns mclk_150k rises, mclk_150k=1
472 ns, Dreg==1'b0, Xin=1
tran: time = 472 ns (3.15 %), step = 117 ns (780 m%)
472 ns, Dreg=x
472 ns, Dreg rises
703 ns, Dreg=1
703 ns, Dreg rises
tran: time = 1.15 us (7.67 %), step = 150 ns (1 %)
tran: time = 1.889 us (12.6 %), step = 150 ns (1 %)
tran: time = 2.639 us (17.6 %), step = 150 ns (1 %)
2900ns mclk_150k rises, mclk_150k=1
3001 ns, Dreg==1'b1, Xin=1
3002 ns, Dreg=x
3002 ns, Dreg falls
3002 ns, Dreg=0
3002 ns, Dreg falls
tran: time = 3.468 us (23.1 %), step = 150 ns (1 %)
tran: time = 4.218 us (28.1 %), step = 150 ns (1 %)
tran: time = 4.968 us (33.1 %), step = 150 ns (1 %)
tran: time = 5.718 us (38.1 %), step = 150 ns (1 %)
6000 ns, Dreg==1'b0, Xin=1
6001 ns, Dreg=x
6001 ns, Dreg rises
6001ns mclk_150k rises, mclk_150k=x
6001 ns, Dreg=1
6001 ns, Dreg rises
6001ns mclk_150k rises, mclk_150k=1
tran: time = 6.467 us (43.1 %), step = 150 ns (1 %)
tran: time = 7.217 us (48.1 %), step = 150 ns (1 %)
tran: time = 7.967 us (53.1 %), step = 150 ns (1 %)
8700ns mclk_150k rises, mclk_150k=1
tran: time = 8.717 us (58.1 %), step = 150 ns (1 %)
9001 ns, Dreg==1'b1, Xin=1
9002 ns, Dreg=x
9002 ns, Dreg falls
9002 ns, Dreg=0
9002 ns, Dreg falls
tran: time = 9.468 us (63.1 %), step = 150 ns (1 %)
tran: time = 10.22 us (68.1 %), step = 150 ns (1 %)
tran: time = 10.97 us (73.1 %), step = 150 ns (1 %)
tran: time = 11.72 us (78.1 %), step = 150 ns (1 %)
12000 ns, Dreg==1'b0, Xin=1
12001 ns, Dreg=x
12001 ns, Dreg rises
12001ns mclk_150k rises, mclk_150k=x
12001 ns, Dreg=1
12001 ns, Dreg rises
12001ns mclk_150k rises, mclk_150k=1
tran: time = 12.47 us (83.1 %), step = 150 ns (1 %)
tran: time = 13.22 us (88.1 %), step = 150 ns (1 %)
tran: time = 13.97 us (93.1 %), step = 150 ns (1 %)
14500ns mclk_150k rises, mclk_150k=1
tran: time = 14.72 us (98.1 %), step = 150 ns (1 %)
Number of accepted tran steps = 158
Initial condition solution time: CPU = 1 ms, elapsed = 631.094 us.

**** AMSD: Mixed-Signal Activity Statistics ****
Number of A-to-D events: 16
Number of A-to-D events in IEs: 16
Number of D-to-A events: 0
Number of D-to-A events in IEs: 0
Number of VHDL-AMS Breaks: 0

Title: Re: E2L convert one analog rising edge into two edges in digital domain
Post by ywguo on Sep 18^th, 2011, 10:07pm

After the rise/fall time of mclk_150k was reduced to 0.1ns, divider-by-2 works. The following is part of simulation log and waveforms.

Code:

Warning from spectre in `cds_globals', during circuit read-in.
`cds_globals': Parameter `power' redefines parameter of same name defined
at higher level.
`cds_globals': Parameter `Ts' redefines parameter of same name defined at
higher level.

Circuit inventory:
nodes 4
csmc05mm01_connectLib+E2L_2_inhconn+module+0x10000001 behavioral 2
vsource 4

************************************************
Transient Analysis `tran': time = (0 s -> 15 us)
************************************************
0 ns, Dreg==1'b1, Xin=1
0 ns, Dreg=0
0 ns, Dreg==1'b1, Xin=1
0 ns, Dreg=0
0ns mclk_150k rises, mclk_150k=0
0ns mclk_150k rises, mclk_150k=0
Important parameter values:
start = 0 s
outputstart = 0 s
stop = 15 us
step = 15 ns
maxstep = 150 ns
ic = all
skipdc = no
reltol = 100e-06
abstol(I) = 1 pA
abstol(V) = 1 uV
temp = 27 C
tnom = 27 C
tempeffects = all
errpreset = conservative
method = gear2only
lteratio = 10
relref = alllocal
cmin = 0 F
gmin = 1 pS

0 ns, Dreg==1'b0, Xin=1
0 ns, Dreg=1
0 ns, Dreg rises
0ns mclk_150k rises, mclk_150k=1
472 ns, Dreg==1'b0, Xin=1
tran: time = 472 ns (3.15 %), step = 139.5 ns (930 m%)
472 ns, Dreg=x
472 ns, Dreg rises
703 ns, Dreg=1
703 ns, Dreg rises
tran: time = 1.15 us (7.67 %), step = 150 ns (1 %)
tran: time = 1.889 us (12.6 %), step = 150 ns (1 %)
tran: time = 2.639 us (17.6 %), step = 150 ns (1 %)
2900ns mclk_150k rises, mclk_150k=1
3000 ns, Dreg==1'b1, Xin=1
3000 ns, Dreg=0
3000 ns, Dreg falls
tran: time = 3.386 us (22.6 %), step = 150 ns (1 %)
tran: time = 4.136 us (27.6 %), step = 150 ns (1 %)
tran: time = 4.886 us (32.6 %), step = 150 ns (1 %)
tran: time = 5.636 us (37.6 %), step = 150 ns (1 %)
6000 ns, Dreg==1'b0, Xin=1
6000 ns, Dreg=1
6000 ns, Dreg rises
6000ns mclk_150k rises, mclk_150k=1
tran: time = 6.386 us (42.6 %), step = 150 ns (1 %)
tran: time = 7.136 us (47.6 %), step = 150 ns (1 %)
tran: time = 7.886 us (52.6 %), step = 150 ns (1 %)
tran: time = 8.636 us (57.6 %), step = 150 ns (1 %)
8700ns mclk_150k rises, mclk_150k=1
9000 ns, Dreg==1'b1, Xin=1
9000 ns, Dreg=0
9000 ns, Dreg falls
tran: time = 9.386 us (62.6 %), step = 150 ns (1 %)
tran: time = 10.14 us (67.6 %), step = 150 ns (1 %)
tran: time = 10.89 us (72.6 %), step = 150 ns (1 %)
tran: time = 11.64 us (77.6 %), step = 150 ns (1 %)
12000 ns, Dreg==1'b0, Xin=1
12000 ns, Dreg=1
12000 ns, Dreg rises
12000ns mclk_150k rises, mclk_150k=1
tran: time = 12.39 us (82.6 %), step = 150 ns (1 %)
tran: time = 13.14 us (87.6 %), step = 150 ns (1 %)
tran: time = 13.89 us (92.6 %), step = 150 ns (1 %)
14500ns mclk_150k rises, mclk_150k=1
tran: time = 14.64 us (97.6 %), step = 150 ns (1 %)
Number of accepted tran steps = 176
Initial condition solution time: CPU = 1 ms, elapsed = 601.053 us.

**** AMSD: Mixed-Signal Activity Statistics ****
Number of A-to-D events: 16
Number of A-to-D events in IEs: 16
Number of D-to-A events: 0
Number of D-to-A events in IEs: 0
Number of VHDL-AMS Breaks: 0

Title: Re: E2L convert one analog rising edge into two edges in digital domain
Post by ywguo on Sep 19^th, 2011, 6:53pm

Now I figure out the cause of that problem. The values are reloaded in ConnRules_inhconn.vams. In the built-in connectLib, Tr is 0.4ns, txdel is 1.6ns. But in my connectLib, tr is 0.04ns and txdel is 0.16ns.

The following is copied from the built in connectLib.

`define Tr 0.4n
`define DelayX `Tr*4
... ...
connect E2L_2_inhconn #( .vsup_min(`VsupMin), .vthi(`Vthi), .vtlo(`Vtlo), .tr(`Tr), .tf(`Tr), .txdel(`DelayX) );

The following is copied from my connectLib.
`define Trcmos 0.04n
`define Trcml 0.02n
... ...
connect E2L_2_inhconn #( .vthi(`Vthi), .vtlo(`Vtlo), .tr(`Trcmos) );

Best Regards,
Yawei