The Designer's Guide Community Forum

The Designer's Guide Community Forum
https://designers-guide.org/forum/YaBB.pl
Other CAD Tools >> Physical Verification, Extraction and Analysis >> layout to schematic problem
https://designers-guide.org/forum/YaBB.pl?num=1317106580

Message started by lanfird on Sep 26^th, 2011, 11:56pm

Title: layout to schematic problem
Post by lanfird on Sep 26^th, 2011, 11:56pm

If I want to use parasitic capacitors of layout instead of mimcap offered by the process, how should I pass LVS? The problem is that when I extract layout capacitor to schematic capacitor (which is a capacitor not provided by the process), I could't get LVS passed.

Title: Re: layout to schematic problem
Post by ywguo on Sep 30^th, 2011, 7:30am

What do you mean by parasitic caps? What is the structure? Generally I think you need SPICE model, and LVS model for it. It is better that there is a pcell.
-- Yawei