The Designer's Guide Community Forum

The Designer's Guide Community Forum
https://designers-guide.org/forum/YaBB.pl
Design Languages >> Verilog-AMS >> HOw to declare a bit
https://designers-guide.org/forum/YaBB.pl?num=1317279888

Message started by zahrein on Sep 29^th, 2011, 12:04am

Title: HOw to declare a bit
Post by zahrein on Sep 29^th, 2011, 12:04am

Hi

Is this how you declare a bit?
real d_enable =1b'1;

CODE

module measure_voh_vol (pad,data);

input pad;
//input d_enable;
input data;

parameter real voh=0.9;
parameter real vol=0.3;
real d_enable =1b'1;

Title: Re: HOw to declare a bit
Post by Geoffrey_Coram on Oct 7^th, 2011, 7:42am

Without thinking too hard about it, I would have said

integer d_enable = 1b'1;

Title: Re: HOw to declare a bit
Post by boe on Oct 7^th, 2011, 8:08am

In Verilog(-AMS) integers are (at least) 32 bit wide. If you want a single bit you should use a reg/wire.
-B O E