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Design Languages >> Verilog-AMS >> My first behaviour model . A linear voltage.
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Message started by zahrein on Oct 3^rd, 2011, 6:45pm

Title: My first behaviour model . A linear voltage.
Post by zahrein on Oct 3^rd, 2011, 6:45pm

I manage to design a VHDL AMS on a linear voltage. The voltage is not linear at all but maybe some improvement on the step size or timing.

The behaviour model is equated as V=IR.
In this VHDL AMS, i fix the current and vary the resistor. Hence we will get the Linear voltage.

The code

Testbench

module tb_test_ver(); //testbench module name

wire pina, pinb; // declaring wire input

basic_models_circuit out1 (.p(pinb) );

initial $vcdpluson; //log on vpd file for dve
initial #(50000) $finish; //set to run for 50,000ps

endmodule
////////////////////////////////////////////////////////////////

Verilog AMS

module basic_models_circuit (p);

parameter real I =1m;
real rinput;
integer i;
output p;
electrical p;

initial begin
for (i =0; i <4000; i=i+100) begin
#1000 ;
rinput = i;

end
end
analog begin
V(p) <+ rinput* I;
end

endmodule
////////////////////////////////////////////////////////////////////