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https://designers-guide.org/forum/YaBB.pl Design Languages >> Verilog-AMS >> Output of a sine wave generator is 0. https://designers-guide.org/forum/YaBB.pl?num=1317804788 Message started by zahrein on Oct 5th, 2011, 1:53am |
Title: Output of a sine wave generator is 0. Post by zahrein on Oct 5th, 2011, 1:53am HI , Im trying to model a sin wave generator. And seems nothing is out from the waveform. Copied my testbench and verilog. Do give me your opinion. Appreciate a lot. Thanks Testbench module tb_test_ver(); //testbench module name wire pina, pinb; // declaring wire input sine_wave out2(.wave(pinb)); initial $vcdpluson; //log on vpd file for dve initial #(50000000000) $finish; //set to run for 50,000ps endmodule Verilog code for sine wave generator module sine_wave (wave); output wave; real offset; electrical wave; parameter real freq = 1000 from (0:inf); parameter real ampl= 1; analog begin V(wave) <+ ampl * sin(3.142* freq * $abstime); $bound_step(0.05/freq); end endmodule |
Title: Re: Output of a sine wave generator is 0. Post by boe on Oct 6th, 2011, 3:46am Hi zahrein, your sine generator seems OK to me. Note that it runs with 500 Hz, so 50 ns is not very much. Are you sure that $vcdpluson supports electrical signals? B O E PS: Which simulator do you use? |
Title: Re: Output of a sine wave generator is 0. Post by zahrein on Oct 6th, 2011, 6:36pm Yes, Boe. Thanks for explaining the mistakes. I fix my verilog and it can can run. Heres the code. And im running on DVE, this is a part of the VCS system at my company. module sine_wave (wave); output wave; real offset; electrical wave; parameter real freq = 1G; parameter real ampl= 1; analog begin V(wave) <+ ampl * sin(3.142* freq * $abstime); $bound_step(0.00001/freq); end endmodule |
Title: Re: Output of a sine wave generator is 0. Post by Ken Kundert on Oct 6th, 2011, 8:48pm Your $bound_step() will force the analog kernel to take 100K points per cycle, which is absurd. You'd be much better served using $bound_step(0.1/freq). -Ken |
Title: Re: Output of a sine wave generator is 0. Post by boe on Oct 7th, 2011, 1:20am Zahrein, Note that in the analog section of Verilog-AMS code the units are given in the include file disciplines.vams, usually Volt, Ampere, second, .... And the timescale directive has no effect for the analog stuff. This is the reason for the $bound_step issue Ken pointed out. B O E |
Title: Re: Output of a sine wave generator is 0. Post by Geoffrey_Coram on Oct 7th, 2011, 7:38am pi is 3.142 ?? Ugh. Why not use `M_PI from `include "constants.vams" ? |
Title: Re: Output of a sine wave generator is 0. Post by boe on Oct 7th, 2011, 8:39am BTW, it should be 2π (`M_TWO_PI). -B O E |
Title: Re: Output of a sine wave generator is 0. Post by zahrein on Oct 8th, 2011, 1:43am HI Boe & Geoffrey_Coram & ken, Thanks for pointing out. The reason i did not use the constant M_PI is to check my code. I increase the bound step is to check wether it has an impact on my sine wave or not as my sine wave look not so smooth. I thought by increasing the bound step will make my sine wave to be smoother. Thanks... |
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