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Design >> Analog Design >> bgap reference circuit (patent architecture)
https://designers-guide.org/forum/YaBB.pl?num=1318091884

Message started by student_of_analog on Oct 8^th, 2011, 9:38am

Title: bgap reference circuit (patent architecture)
Post by student_of_analog on Oct 8^th, 2011, 9:38am

Hello all,

I was having some problems understanding what M1 and RB are used for in the attached bandgap schematic.
I understand the rest of the circuitry.

In a typical bandgap circuit, the output of the opamp goes to a current mirror, and Vbg is taken at the output (Drain) of the current mirror.
In this patent, the output of opamp is driving a CS transistor whose load is RB, I do not understand how this circuit works.

Can anybody help me understand this.

Title: Re: bgap reference circuit (patent architecture)
Post by RobG on Oct 9^th, 2011, 12:59pm

The voltages across RA1 and RA2 are the same so they acts as a mirror. RB is not needed, but then RA1 and RA2 would have to be larger, so RB saves space at a cost of increased sensitivity to opamp offset. Together, the voltage across RA1 (or RA2) plus the voltage across RB make up the PTAT portion of the bandgap voltage.

M1 can be thought of as the output device of the opamp. One of the advantages of this topology is that it can source current to the load. Making the mirror using resistors instead of MOSFETs also results in less thermal noise.

Title: Re: bgap reference circuit (patent architecture)
Post by student_of_analog on Oct 10^th, 2011, 12:38pm

Thank you Rob..
now I have trouble identifying positive feedback loop and negative feedback loop for this architecture.
So, just for analysis if I break the loop going to the + terminal of the opamp and I look at the loop
connected to the - terminal of the opamp, it looks like the loop connected to the - terminal has positive feedback...
but isn't this loop supposed to be negative feedback ?
am I analysing it wrong...
if V- increaes, error voltage difference at opamp input decreaes, therefore output of opamp decreases, therefore output if M1 increases
which means V- increases again --- > positive feedback ??

Title: Re: bgap reference circuit (patent architecture)
Post by rfcooltools.com on Oct 10^th, 2011, 2:09pm

student_of_analog

The Mosfet M1 current is the inversely proportional of the opamp voltage. So negative feedback is achieved.

http://rfcooltools.com

Title: Re: bgap reference circuit (patent architecture)
Post by RobG on Oct 10^th, 2011, 4:43pm

Actually it looks like the polarity of the opamp is incorrect in the figure when you account for the inversion through the PMOS device. The negative fb leg should be through RA1, but the figure shows that path to be positive if you take the figure literally.

Title: Re: bgap reference circuit (patent architecture)
Post by student_of_analog on Oct 10^th, 2011, 8:44pm

Thank you RobG,

That was what was putting me off track...so is right to assume that the terminals are incorrect in the patent ?
or is there something else that is going on, that I have not been
able to see ?

Title: Re: bgap reference circuit (patent architecture)
Post by rfcooltools.com on Oct 10^th, 2011, 11:01pm

I believe RobG is right on second glance.

http://rfcooltools.com

Title: Re: bgap reference circuit (patent architecture)
Post by RobG on Oct 11^th, 2011, 9:44am

rfcooltools.com wrote on Oct 10^th, 2011, 11:01pm:

I believe RobG is right on second glance.

http://rfcooltools.com

I didn't see it at first. It usually takes me 3-4 times to get the polarity right on these things :)

Student_of_analog - just remember the feedback from the delta-Vbe side to the output has to be negative for it to start-up. Typically, the PMOS is the 2nd stage of miller compensated amplifier, so the "opamp" in the figure is a single stage with the polarity opposite of what is shown.

Title: Re: bgap reference circuit (patent architecture)
Post by loose-electron on Oct 13^th, 2011, 1:25pm

3 or 4?

LOL! Out of 2 options?

That patent is not going to survive a court challenge.
That architecture has been around at least 15 years or more.

Title: Re: bgap reference circuit (patent architecture)
Post by RobG on Oct 13^th, 2011, 1:30pm

loose-electron wrote on Oct 13^th, 2011, 1:25pm:

3 or 4?

LOL! Out of 2 options?

That patent is not going to survive a court challenge.
That architecture has been around at least 15 years or more.

Well I farm out the work on the first two ;)
It seems like they will patent anything. I used the same type of cap cancellation about 15 years ago... but I was using it so that the injected substrate noise was common mode.

Title: Re: bgap reference circuit (patent architecture)
Post by Alexandar on Oct 14^th, 2011, 12:28am

How do you mean capacitance cancellation? Isn't it the resistor in the base that reduces the sensitivity to ground noise/injection?

Funny that such a structure can be patented (again). If I recall correctly I've seen this circuit multiple times. But Mr. Ranucci apparently found another way of describing it... just proves again how incapable the patent examiners are..

Title: Re: bgap reference circuit (patent architecture)
Post by RobG on Oct 14^th, 2011, 6:54am

Alexandar - The AC noise on the substrate will couple into the circuit via the caps on the bipolars. Since the left bipolar is larger than the right, the left AC current is larger than the right. The bipolars distort the current (partially rectify it). The distortion includes a DC component. Since the DC components are different on the right and left there will be a new DC operating point. The end result is that the DC value of the bandgap will change in the presence of AC noise.

On the other hand, if you balance the caps on each side the AC noise injected into the circuits will be the same. Since the AC noise is the same, the rectified current will be balanced and the operating point will remain the same.

Title: Re: bgap reference circuit (patent architecture)
Post by Alexandar on Oct 16^th, 2011, 11:49pm

I understand your explanation but I'm not completely following the solution you propose. By caps on the BJT, are you referring to Cbe? So you're suggesting placing dummy bipolar caps between base/emitter, such that both legs see the same Cbe capacitance?

BTW Is there anything wrong with placing an additional resistor from base of the BJTs to the ground? Besides in the opening post of this topic, I've seen that in several designs so far, and it should reduce sensitivity to ground/substrate noise as well...

Title: Re: bgap reference circuit (patent architecture)
Post by RobG on Oct 17^th, 2011, 7:15am

No, in this case you are matching the depletion cap from substrate to base. The detailed description of the patent explains this better than I can, and is actually quite readable. I think there should actually be 38 caps on the right side for proper matching, but I assume that 32 was chosen because it gives a symmetric layout.

The base-emitter depletion caps should also be matched but they must be much smaller than the depletion caps of the base/collector or this would not have worked as I've explained. (Nor would it work if you weren't gaining up the voltage with R1 and R2. I don't remember doing matching Cbe, but the more I think back, the more I realize I forgot exactly what I did!

I'm not sure what you mean by tying an additional base resistor to ground - are you trying to match the base resistors? That's ok when the base is tied to ground, but that won't work at all in this circuit (R2 is already there). The base resistance in the figure is intentional: it nulls out the effect of base current drop in the R1/R2 network. Eq. 12 gives the value. Again, the patent talks about this in the explanation.

rg