The Designer's Guide Community Forum

The Designer's Guide Community Forum
https://designers-guide.org/forum/YaBB.pl
Design Languages >> VHDL-AMS >> Question on VHDL-AMS modeling?
https://designers-guide.org/forum/YaBB.pl?num=1318356854

Message started by ethanlinear on Oct 11^th, 2011, 11:14am

Title: Question on VHDL-AMS modeling?
Post by ethanlinear on Oct 11^th, 2011, 11:14am

I am confused with isj_out. It is not on the port list and never has an initial value, but there is a line,

vsj_out == vsj_int + isj_out * 50.0;

What is the purpose for isj_out here? I am trying to convert VHDL-AMS code into Verilog-AMS code, how can I do it? thanks,

architecture bhv of sj_src is
constant sj_tau : time := 10ps;
quantity vsj_out across isj_out through sj_out;
quantity vsj_int : voltage;
begin
-- All quantities considered in a 50 Ohm environment
-- Voltage source is 2 * effective voltage
-- sj_amp is considered a PP voltage
-- output signal is centered around Vdd/2=0.0V
vsj_int == 2.0 * (0.0 + 0.9 * 0.5 * sj_amp * sin(MATH_2_PI*sj_freq*freq*NOW));
vsj_out == vsj_int + isj_out * 50.0;
end bhv;

Title: Re: Question on VHDL-AMS modeling?
Post by Ken Kundert on Oct 11^th, 2011, 9:26pm

isj_out appears to the the current through sj_out. Looks like the voltage source in series with a 50Ω resistor.

-Ken