The Designer's Guide Community Forum

The Designer's Guide Community Forum
https://designers-guide.org/forum/YaBB.pl
Design >> Analog Design >> about LDO speed problems
https://designers-guide.org/forum/YaBB.pl?num=1318845044

Message started by sean.geng on Oct 17^th, 2011, 2:50am

Title: about LDO speed problems
Post by sean.geng on Oct 17^th, 2011, 2:50am

Hi, all,

i would like to propose a question about LDO speed, and i am always confused about this.

below is my schematic.

and i want to ask everyone that, according to my thoughts, the speed up circuit will accelerate settling behavior whenever the output of OPAMP increases or decreases. however, the simulation results just prove it is right when the output of OPAMP increases. and when in decreasing condition, it will be slower than without the circuit.

so, can anybody tell me what's wrong?

Title: Re: about LDO speed problems
Post by sean.geng on Oct 17^th, 2011, 8:08pm

no replies?

Title: Re: about LDO speed problems
Post by Praveen K on Oct 17^th, 2011, 11:13pm

hi Sean,

Can't really grasp your circuit. Assuming that the top PMOS switch beside the speedup circuit is off, can't understand how the speedup circuit is really speeding up.

1. your speedup branch is killing the gain of the opamp because of that diode connected NMOS at the bottom(connected to opamp output).
2. again you are killing the gain for the mirror with a parallel resistor.

Or you killing the DC gain so as to get a larger UGB?

even if this speedup works, you are controlling only the charging path of the output cap. your discharge path is just controlled by that resistor and two diode connected NMOS at the output.

just curious, what is the DC gain of this circuit?

k.praveen

Title: Re: about LDO speed problems
Post by sean.geng on Oct 18^th, 2011, 2:46am

Hi, Praveen,

1. the gain consist 2 parts: (1) the gain of OPAMP, as you referred, the gain of OPAMP is small, because we want a faster settling behavior, and adding two diode-connected mos would be helpful.(2) the GM of regulated NMOS and resistance at output node.

2. this gain would reach 80db even there are some diode-connected MOS at the output of OPAMP.

3. my thought is that:
when the output voltage of OPAMP varies, the speed up branch will provide another small signal current to the drain of regulated NMOS.
you can think it as another gm provider as what regulated NMOS does.

4.and there are some problems:
(1) this branch only increases the speed when the output voltage of OPAMP increases, otherwise, it is worse.
(2) the line regulation would be worse if the gain from VDD to the output of OPAMP is larger than the gain of OPAMP.

Title: Re: about LDO speed problems
Post by sean.geng on Oct 18^th, 2011, 2:48am

and i didn't understand what you said exactly.
Praveen K wrote on Oct 17^th, 2011, 11:13pm:

Title: Re: about LDO speed problems
Post by raja.cedt on Oct 18^th, 2011, 3:19am

hello,
why don't you post a simple schematic or some sts simulator based schematic. I thins schematic is very difficult to understand.

Are you driving switching load, if so regulator will try to settle whenever current drawn from regulator, so if you want to increase the UGB during this settling, why don't you increase the amplifier tail current. Up to my knowledge speed is depends on UGB, doesn't matter how much DC gain up to some extent.

Thanks,
raj.

Title: Re: about LDO speed problems
Post by Alexandar on Oct 19^th, 2011, 12:30am

sean.geng wrote on Oct 17^th, 2011, 2:50am:

and i want to ask everyone that, according to my thoughts, the speed up circuit will accelerate settling behavior whenever the output of OPAMP increases or decreases. however, the simulation results just prove it is right when the output of OPAMP increases. and when in decreasing condition, it will be slower than without the circuit.

so, can anybody tell me what's wrong?

I agree that the speed should increase either way. Maybe it is some problem in the biasing? Maybe it is some speed related issue? Did you check what happens to the 'gate' voltage in your design when going up and down? And check the gatevoltages of the transistors driving that node (the PMOS and NMOS).

On a side note, maybe u could provide a clear schematic, because the text and numbers are barely readable. At least it would make it clear whether u use long/short devices and so on.

Title: Re: about LDO speed problems
Post by loose-electron on Oct 23^rd, 2011, 7:36pm

clarification of circuits, what they do and what you are trying to do would be helpful