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Simulators >> Circuit Simulators >> HSPICE stateye analyse
https://designers-guide.org/forum/YaBB.pl?num=1319786646

Message started by haykp on Oct 28^th, 2011, 12:24am

Title: HSPICE stateye analyse
Post by haykp on Oct 28^th, 2011, 12:24am

Dear Forum,

Please help me understand what does the HSPICE stateye analyze.
I am running stateye on some op amp and there are some parms which I cannot understand in that analyze, those are
1) port instance
2) incident and probe

Any book, article will be helpful.

Thansk,
Hayk

Title: Re: HSPICE stateye analyse
Post by raja.cedt on Oct 28^th, 2011, 1:46am

hello,
is stateye is for serial link simulations or any generic tool? because for SERDES i have used this, but you said for opamps.. how come?

Thanks,
Raj.

Title: Re: HSPICE stateye analyse
Post by haykp on Oct 28^th, 2011, 5:04am

Hi Raj,

Frankly speaking don't know. I have found some example where stateye analyze is done on some Op-Amp circuit.

But if you are familiar with SerDes, then could you please help me understand what is stateye, how to run it and read eye diagrams.
( Like you perfectly explained me in the last time :) )

Any book or article would be helpful.

Thanks in advance for you help.

Title: Re: HSPICE stateye analyse
Post by raja.cedt on Oct 28^th, 2011, 5:26am

hello,
Please find the attached doc, which may be helpfull. But could you show me where did you find opamp with stateye.

Thanks,
Raj.

Title: Re: HSPICE stateye analyse
Post by haykp on Oct 28^th, 2011, 5:44am

Dear Raj,

Thanks for the file.

Please see the attached screenshot, where is the test-bench of opAmp on which statetye is run.

Title: Re: HSPICE stateye analyse
Post by haykp on Oct 31^st, 2011, 3:24am

Hi Raja,

Would you please point me some other, more simple, doc where I can read about stateye analyze.

Seems I need to gain more basics on this prior reading the attached doc.

Thanks,
Hayk